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Storage device and method for processing data

A storage device and data processing technology, applied in the direction of input/output to record carrier, etc., can solve the problem of performance degradation of flash memory

Active Publication Date: 2019-03-01
SLICONGO MICROELECTRONICS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, when overwriting large data on storage blocks, it is often necessary to select the blocks in the storage area and back up the data that does not need to be overwritten in each block to the cache area to reclaim the blocks in these storage areas before performing new operations. Data writing, the more data recovered, the performance of flash memory will decrease

Method used

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  • Storage device and method for processing data
  • Storage device and method for processing data
  • Storage device and method for processing data

Examples

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Embodiment Construction

[0033] Below in conjunction with accompanying drawing and preferred embodiment the present invention is described in further detail:

[0034] Please refer to figure 1 and figure 2 , the storage device 100 of the present invention includes a buffer area 110 and a storage area 120 . The cache area 110 includes a logical processing block 30 . The logical processing block 30 includes a recording unit 31 , a sorting unit 33 and an output unit 35 .

[0035] In this embodiment, the storage device 100 is a flash memory, the cache area 110 is a single-level unit mode, and the storage area 120 is a multi-level unit mode, wherein the storage area 120 is a three-level unit mode.

[0036] The recording unit 31 is used for recording the logical block address corresponding to each cache block in the cache area 110 . Wherein, the logical block address is the total address of the logical address of each block after the logical address of the data is divided into several blocks. For examp...

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Abstract

The invention discloses a storage device which comprises a logic processing block, wherein the logic processing block comprises a recording unit, a sequencing unit and an output unit; the recording unit is used for recording a logic block address corresponding to each cache block stored in a cache area in the storage device; the sequencing unit is used for sequencing the recorded logic block addresses; the output unit is used for outputting the cache blocks to a storage area in the storage device according to corresponding logic block addresses. The storage device disclosed by the invention is used for storing the cache blocks in the storage area in the sequence of the logic addresses of the cache blocks when the cache blocks need to be transferred to the storage area from a cache area, relevance of data of each storage block in the storage area is improved, the recycling loss of the storage blocks is reduced in large file covering writing, and the writing and reading performance of the storage device is improved. The invention further discloses a data processing method of the storage device.

Description

technical field [0001] The invention relates to a storage device and a data processing method thereof. Background technique [0002] There are single-level cell mode (SLC, Single-Level cell) and multi-level cell mode (MLC, Multi-Level cell) in the physical block of flash memory (Flash), and described multi-level cell mode comprises three-level cell mode (TLC, Triple-Level cell) Level cell). Usually, in the flash memory, the SLC area is used as a cache area, and the TLC area is used as a storage area. When data is dumped from the cache area to the storage area, the data of any three blocks in the cache area will be dumped into one block in the storage block. In this way, when overwriting large data on storage blocks, it is often necessary to select the blocks in the storage area and back up the data that does not need to be overwritten in each block to the cache area to reclaim the blocks in these storage areas before performing new operations. When data is written, the mo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
Inventor 曹志忠吴大畏李晓强
Owner SLICONGO MICROELECTRONICS INC
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