Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Time domain interleaving analog-digital converter sample time mismatch calibration method and system

An analog-to-digital converter, sampling time technology, applied in the direction of analog-to-digital converter, analog-to-digital conversion, code conversion, etc., can solve the problems of limited calibration accuracy of differentiators, insensitivity to gain mismatch, and increased circuit complexity. , to achieve the effect of high calibration accuracy, simple and easy circuit structure, and avoidance of amplitude errors

Active Publication Date: 2016-08-17
NANJING TIANYI HEXIN ELECTRONICS
View PDF12 Cites 11 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Compared with the single-channel ADC, although the time-domain interleaving ADC has the advantage of speed, it still has some defects: the mismatch between different channels produces clutter signals on the output spectrum, and the channel mismatch mainly includes : There are three types of offset mismatch, gain mismatch, and sampling time mismatch. For an N-channel interleaved analog-to-digital converter, the offset mismatch is at a frequency of m*f ck Noise spectral components are produced at ; the gain mismatch is at frequency m*f ck + / -f in Noise spectral components are generated at ; the sampling time mismatch is also at frequency m*f ck + / -f in Noise spectrum components are generated at (m=1, 2...N, f in is the input signal frequency); in actual design, 8-bit to 10-bit analog-to-digital converters can achieve accurate matching between channels through careful circuit design and layout design, but in more than 10-bit analog-to-digital converters , when higher performance is required, it is necessary to design a specific calibration scheme for mismatch error calibration. In order to avoid the interruption of the operation of the analog-to-digital converter, it is very necessary and desirable to run the calibration in the background
[0009] In order to reduce the calibration range and make the design simple, in the actual design, we only need to obtain the relative sampling time mismatch between different channels rather than the absolute sampling time mismatch relative to the reference channel (the reference channel may vary according to the specific implementation has large timing skew), the method is not sensitive to gain mismatch mainly due to the fact that S n *S ref is the cross-correlation of the derivative of the input signal and the input signal, and its value is close to zero if the sampling time of the reference channel and the calibration channel are exactly the same (the input signal can be seen as the sum of the differential sine wave and the cross-correlation of the sine wave and its derivative to zero), compared to figure 2 method, which is more robust, however, measuring the derivative of the input signal shown is not a trivial task and requires an analog or digital differentiator
But this not only increases the complexity of the circuit, but its calibration accuracy is limited and the accuracy of the differentiator

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Time domain interleaving analog-digital converter sample time mismatch calibration method and system
  • Time domain interleaving analog-digital converter sample time mismatch calibration method and system
  • Time domain interleaving analog-digital converter sample time mismatch calibration method and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] The technical solution of the present invention will be further introduced below in combination with specific embodiments.

[0039] The invention discloses a method for calibrating the sampling time mismatch of a time-domain interleaved analog-to-digital converter, which includes the following steps:

[0040] S1: Add a reference channel in addition to the N standard channels of the analog-to-digital converter to form a total of N+1 channels;

[0041] S2: The output data of each channel is sent to the sampling time mismatch coefficient extraction circuit 1, and the control coefficient of the adjustment circuit is extracted and sent to the sampling time adjustment control circuit 2;

[0042] The adjustment circuit control coefficient is calculated by formula (1):

[0043] CTS k+1 =CTS k -u*(e k -e k-1 )*sign(CTS k -CTS k-1 ) (1)

[0044] In formula (1), CST is the control coefficient of the adjustment circuit, u is the iterative step coefficient of the approximati...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention discloses a time domain interleaving analog-digital converter sample time mismatch calibration method and system. The system includes N standard channels and a reference channel, a sample time mismatch coefficient extracting circuit, and a sample time adjustment control circuit. Adjustment circuit control coefficients of a to-be-calibrated standard channel and a to-be-calibrated reference channel are extracted by the sample time mismatch coefficient extracting circuit, the adjustment circuit control coefficients are transmitted to the sample time adjustment control circuit, and the sample time adjustment control circuit controls a sample clock of the to-be-calibrated standard channel. Through adoption of the time domain interleaving analog-digital converter sample time mismatch calibration method and system, sample time calibration is not affected by amplitude errors, the circuit structure is simple to implement, a differentiator is not needed, and the method is rapid in convergence, has high calibration accuracy, and is not affected by signal amplitude and gain mismatch.

Description

technical field [0001] The invention relates to the field of background calibration, in particular to a calibration method and system for sampling time mismatch of a time-domain interleaving analog-to-digital converter. Background technique [0002] Employing a time-domain interleaved pattern is an easy way to significantly increase the effective sampling rate of an analog-to-digital converter (ADC), figure 1 shows a typical time-domain interleaved ADC consisting of N identical ADC channels, each clocked at f ck , but the sampling time is staggered by Tck / N, therefore, the overall sampling rate of the N-channel ADC is equivalent to a clock frequency of f ck *N single-channel ADC with a sampling time of 1 / (f ck *N). Obviously, the chip area and power consumption of this interleaved ADC are N times that of the single-channel ADC. However, when the single-channel ADC is difficult to achieve a high sampling rate (limited and manufacturing process), in These are acceptable wh...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H03M1/08H03M1/12
CPCH03M1/08H03M1/121Y02D30/70
Inventor 李纪鹏
Owner NANJING TIANYI HEXIN ELECTRONICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products