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FPGA-based IRIG-B(DC) fast decoding method

A decoding method and fast technology, applied in pulse conversion and other directions, can solve problems such as difficult debugging, large volume, and low integration

Inactive Publication Date: 2016-07-13
YUNNAN POWER GRID CO LTD ELECTRIC POWER RES INST +1
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Problems solved by technology

[0002] At present, the IRIG-B code time unification system developed and developed by discrete components has disadvantages such as complex circuit, low integration, difficult debugging, large volume, high cost, and low confidentiality. With the rapid development of information technology revolution and computer technology , programmable logic technology has matured

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  • FPGA-based IRIG-B(DC) fast decoding method
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  • FPGA-based IRIG-B(DC) fast decoding method

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Embodiment Construction

[0015] The embodiment of the present invention will be described in further detail below in conjunction with the accompanying drawings, and the following specific implementation content and figure 2 The realization schematic diagram of fast decoding of IRIG-B (DC) code will be included in the protection scope of the present invention.

[0016] IRIG-B (DC) code (referred to as B code) is a BCD serial time code, each symbol width is 10ms, which is pulse width code (such as figure 1 As shown, the pulse width 2ms, 5ms and 8ms respectively represent the binary "0", "1" and the time frame reference mark P R or position identification mark P). A time frame period includes 100 symbols, and the "punctual" reference point of a symbol is its pulse leading edge, starting from the time frame reference mark P R Counting from the beginning, there is a position identification mark P every 10 symbols, and their pulse width is 8ms. Therefore, two consecutive pulses with a pulse width of 8ms...

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Abstract

An FPGA-based IRIG-B(DC) fast decoding method is disclosed and the method comprises an IRIG-B(DC) fast decoding step and a step of sending decoding messages via serial ports after the decoding messages are packeted. According to the FPGA-based IRIG-B(DC) fast decoding method, via use of FPGA technologies, on-line data monitoring technologies, serial port communication technologies and the like, defects of a conventional IRIG-B code time unification system developed via use of discrete elements can be address, wherein the defects of the conventional IRIG-B code time unification system is are circuit complexity, low integration level, difficult-to-debug characteristic, large size, high cost, low confidentiality and the like; most requirements for precision can also be met by the FPGA-based IRIG-B(DC) fast decoding method.

Description

technical field [0001] The invention belongs to the technical field of an FPGA-based IRIG-B (DC) fast decoding method Background technique [0002] At present, the IRIG-B code time unification system developed and developed by discrete components has disadvantages such as complex circuit, low integration, difficult debugging, large volume, high cost, and low confidentiality. With the rapid development of information technology revolution and computer technology , Programmable logic technology has matured. In order to achieve precise synchronization between IRIG-B code and time signal, stable performance, small integration volume and low manufacturing cost, a fast decoding method of IRIG-B(DC) code based on FPGA is proposed. The method realizes IRIG-B (DC) code demodulation to generate 1pps signal and clock message, and the clock message is sent in groups through the serial port. Contents of the invention [0003] The purpose of the present invention is to overcome the de...

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Application Information

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IPC IPC(8): H03M5/04
CPCH03M5/04
Inventor 李孟阳唐立君张林山杨映春
Owner YUNNAN POWER GRID CO LTD ELECTRIC POWER RES INST
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