MOS power device and method for forming same

Abstract

The invention discloses a MOS power device and a method for forming the same. The MOS power device comprises a first conductive type of voltage-withstand layer, a first conductive type of barrier layer on the voltage-withstand layer, a second conductive type of well region in the barrier layer, first conductive type of source regions in the well region, gates on the barrier layer, a first electrode on the gates and the barrier layer, and a second electrode under the voltage-withstand layer, wherein the barrier layer comprises multiple barrier child layers, the first barrier child layer wraps the well region, the (i+1)th barrier child layer wraps the ith barrier child layer, and the dosage concentration of the ith barrier child layer is greater than that of the (i+1)th barrier child layer. In the MOS power device, the barrier layer is a multi-child-layer structure with gradually changed dosage concentration. Equivalently, multiple barriers are provided so that the on-state voltage drop is decreased, low total amount of doped impurities is achieved, the withstand voltage of the MOS power device cannot be reduced obviously, and a restriction between the on-state voltage drop and the voltage-withstand capability is relieved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a MOS type power device and a forming method thereof. Background technique [0002] MOS type power devices with conductance modulation effect are widely used in medium, high voltage, medium and high frequency fields due to their advantages such as reduced conduction voltage and fast switching speed. Low loss has always been an important goal for the development of semiconductor MOS power devices, and lower conduction voltage drop ensures that MOS power devices have lower conduction losses. For MOS power devices with conductance modulation effect, the near-surface carrier storage technology is an effective means to reduce the on-voltage drop, and the hole blocking layer structure is the most common type of surface carrier storage technology. The specific solution is: introduce a layer of N-type doping region with higher doping concentration than N- in the part...

AI Technical Summary

Problems solved by technology

According to semiconductor theory, the higher the doping concentration, the larger the electric field gradient, and the greater the slope of the electric field distribution in the hole blocking layer. As the depletion layer extends to the N-region, the electric field drops rapidly, resulting in the withstand voltage of MOS power devices. Significantly lower, the conduction voltage drop and the withstand voltage are mutually restricted, and the optimization is limited

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