Coprocessor based on reconfigurable computational array

Abstract

The invention relates to a coprocessor based on a reconfigurable computational array. The coprocessor comprises a main controller which receives control information sent by an external universal processor, then analyzes the control information and sends out a corresponding configuration instruction, a reconfiguration controller which sends out the configuration information according to an algorithm parameter in the configuration instruction, an operation core unit which receives the configuration information and completes basic computation such as complex multiplication, complex addition and real multiplication, and a DMA unit which receives a transmission parameter of the configuration instruction and carries out data among an external DDR, an internal storage module and the main controller, wherein the configuration instruction comprises the transmission parameter and the algorithm parameter, and the configuration information comprises an execution signal used for selecting and organizing a logic algorithm in the operation core unit and an internal network gating signal. The coprocessor has the advantages of being good in computing performance and small in area consumption.

Description

technical field [0001] The present invention relates to coprocessors for reconfigurable computing arrays. Background technique [0002] With the advancement of science and technology, people have higher and higher requirements for computing performance. High-performance signal processing is widely used in image processing, scientific computing, and industrial control and other fields. In addition, these high-performance signal processing applications involving advanced signal processing technology and intensive computing work have higher requirements for real-time and versatility of the system year by year, and the computing requirements for computing systems are also getting higher and higher. [0003] Existing general-purpose processors, including CPU (Central Processing Unit, central processing unit) and DSP (DigitalSignalProcessing, digital signal processing), can also complete the realization of high-performance signal processing algorithms, but there are still the foll...

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Problems solved by technology

[0003] Existing general-purpose processors, including CPU (Central Processing Unit, central processing unit) and DSP (DigitalSignalProcessing, digital signal processing), can also complete the realization of high-performance signal processing algorithms, but there are still the following problems: general-purpose processors in order to achieve versatility , the structure is relatively complex, and it needs to pay a large power consumption and area cost for floating-point matrix operations. In addition, the characteristics of general-purpose processors executing tasks based on instruction streams make it take too long to implement intensive algorithms.

[0005] Another design idea to improve computing performance is to design dedicated acceleration hardware modules for specific algorithms, such as dedicated FFT modules, matrix inversion modules, and filtering operation modules, etc., but integrating too many acceleration modules in a system will undoubtedly increase the speed. Large hardware resources and area overhead

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