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Fixed-point and floating-point operation part with shared multiplier structure in GPDSP

A floating-point operation and multiplier technology, which is applied in the calculation using the number system and the non-contact manufacturing equipment for calculation, etc. The effect of improving the utilization of hardware resources

Inactive Publication Date: 2016-05-25
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Such a design leads to low hardware reuse rate, large occupied area, and waste of hardware resources

Method used

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  • Fixed-point and floating-point operation part with shared multiplier structure in GPDSP
  • Fixed-point and floating-point operation part with shared multiplier structure in GPDSP
  • Fixed-point and floating-point operation part with shared multiplier structure in GPDSP

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Embodiment Construction

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0039] like figure 1 As shown, the fixed-point floating-point arithmetic unit of the GPDSP shared multiplier structure of the present invention includes a shared 64-bit fixed-point multiplier, a floating-point multiply-add unit MAC (FMAC) and a fixed-point multiply-add unit MAC (IMAC). The floating-point multiplication and addition unit FMAC supports IEEE-754 standard double-precision floating-point operations and IEEE-754 standard SIMD structure double single-precision floating-point multiplication, multiplication and addition, multiplication and subtraction, and complex multiplication operations; the fixed-point multiplication and addition unit IMAC supports 64 1-bit signed or unsigned fixed-point multiply operation and dual 32-bit signed or unsigned fixed-point multiply operation for SIMD structures.

[0040] The GPDSP of the pres...

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Abstract

The invention discloses a fixed-point and floating-point operation part with a shared multiplier structure in a GPDSP (General-Purpose Digital Signal Processor). The fixed-point and floating-point operation part comprises a floating-point multiplier-adder unit, a fixed-point multiplier-adder unit and a 64-bit fixed-point multiplier, wherein the floating-point multiplier-adder unit is used for supporting double-precision floating-point operation and double / single-precision floating point multiplication, multiplication-addition, multiplication-subtraction and complex multiplication operations of an SIMD structure; the fixed-point multiplier-adder unit is used for supporting 64-bit signed or unsigned fixed-point multiplication operation and double 32-bit signed or unsigned fixed-point multiplication operation of the SIMD structure; and the 64-bit fixed-point multiplier performs operation by regarding floating-point mantissa multiplication as unsigned fixed-point multiplication by multiplexing the structure of the same multiplier. The fixed-point and floating-point operation part has the advantages of capabilities of increasing the hardware utilization rate and reducing the chip area, and the like.

Description

technical field [0001] The invention mainly relates to the field of microprocessor structure and design, in particular to a fixed-point floating-point product operation unit with a shared multiplier structure suitable for high-performance general-purpose digital signal processors (General-Purpose Digital Signal Processor, GPDSP for short). Background technique [0002] In the field of traditional digital signal processing, data is usually organized, stored and processed in a fixed-point manner, and traditional DSP provides high fixed-point computing performance for fixed-point computing. However, in modern communication, image processing and radar signal processing and other application fields, with the increase of data processing capacity, data calculation accuracy and real-time requirements, it is usually necessary to use a higher-performance microprocessor. The requirements for data accuracy and real-time performance are also constantly increasing. Due to the high floatin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52
Inventor 雷元武彭元喜韩珊珊陈书明刘宗林田甜胡封林刘祥远刘仲陈海燕王耀华陈虎马胜孙书为许邦建
Owner NAT UNIV OF DEFENSE TECH
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