Storage space multiplexing based method for increasing effective access rate of SDRAM bus

Abstract

The invention discloses a storage space multiplexing based method for increasing an effective access rate of an SDRAM bus. The method comprises the following steps: dividing four 8-bit SDRAM chips into two groups Group0 and Group1, and alternately accessing to the groups Group0 and Group1 in a time sequence by utilizing different chip selection signals based on a memory access command, wherein two SDRAM chips in each group share a chip selection signal; storing table items in an SDRAM as four mirror images in physical Banks, and generating four virtual logic Banks for a user, wherein the four mirror images are located in different physical Banks; and performing arbitrative selection on the logic Banks, and distributing a memory access request of the user to the different physical Banks to realize in-turn access among the physical Banks. According to the method, the activation time and the pre-charging time for each SDRAM access are hidden for the user through bus grouping and multiplexing based on combination of Bank mirror images and Bank arbitration, so that the access rate of the same Bank of the SDRAM is increased to 65Mpps from about 20Mpps, and the access rate requirement of 60Mpps of a 40G platform of a current network device is met.

Description

technical field [0001] The invention relates to the SDRAM field, in particular to a method for increasing the effective access rate of the SDRAM bus based on storage space multiplexing. Background technique [0002] With the continuous and rapid increase of network bandwidth and network data volume, the processing capability requirements of communication equipment at each key node of the network are also continuously increasing. The processing capability of communication equipment is not only reflected in the improvement of the computing power of the chip itself, but also requires a corresponding increase in the unit rate of the chip for storage, reading and writing, input and output of peripheral data. However, the rapid improvement of the chip's ability to access external storage is not always fully synchronized with the performance of the external storage, which has become a bottleneck restricting the performance of the chip to a certain extent. [0003] As one of the im...

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Problems solved by technology

[0010] The technical problem to be solved by the present invention is the problem that the existing ways of improving SDRAM storage access ability are difficult to meet the actual application requirements

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