Shift register and driving method thereof, grid driving circuit, and display apparatus
A technology for shift registers and display devices, which is applied in static memory, digital memory information, instruments, etc., and can solve problems such as complex connection structure, increased process difficulty, and uncompetitive display panels.
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Embodiment 1
[0082] by Figure 2d The structure of the shift register shown is taken as an example to describe its working process, in which Figure 2d In the shift register shown, all switching transistors are P-type switching transistors, and each P-type switching transistor is turned on under the action of a low potential, and is turned off under the action of a high potential; the potential of the DC signal terminal VC is a high potential, and the corresponding The input and output timing diagram is as follows Figure 4a Shown, specifically, select as Figure 4a There are four stages in the shown input-output timing diagram, the first stage T1, the second stage T2, the third stage T3 and the fourth stage T4.
[0083] In the first stage T1, Input=1, CK1=1, CK2=0, CS1=0. Since CK1=1, the first switch transistor M1 is turned off; because CS1=0, both the second switch transistor M2 and the third switch transistor M3 are turned on; The signal of VC is provided to the first node A, so th...
Embodiment 2
[0094] by Figure 3d The structure of the shift register shown is taken as an example to describe its working process, in which Figure 3d In the shift register shown, all switching transistors are N-type switching transistors, and each N-type switching transistor is turned on under the action of a high potential, and is turned off under the action of a low potential; the potential of the DC signal terminal VC is a low potential, and the corresponding The input and output timing diagram is as follows Figure 4b Shown, specifically, select as Figure 4b There are four stages in the shown input-output timing diagram, the first stage T1, the second stage T2, the third stage T3 and the fourth stage T4.
[0095] In the first stage T1, Input=0, CK1=0, CK2=1, CS1=1. Since CK1=0, the first switch transistor M1 is turned off; because CS1=1, both the second switch transistor M2 and the third switch transistor M3 are turned on; The signal of VC is provided to the first node A, so the...
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