UVM (universal verification methodology) based write-only register verification test platform and verification method

Abstract

The invention discloses a UVM (universal verification methodology) based write-only register verification test platform. The UVM based write-only register verification test platform comprises a UVM based test framework and a DUT (device under test) module, wherein the UVM based test framework comprises a UVM test sequence and a UVM sequencer; the DUT module is a digital design module provided with a register and a register read-write bus interface; the UVM based test framework is connected with the DUT module through the register read-write bus interface; the UVM test sequence can call the UVM sequencer, and the UVM sequencer excites the DUT module through the register read-write bus interface according to a test requirement; the UVM test sequence accesses internal signals of the DUT module through a VPI (Verilog programmatic interface). The invention further discloses a UVM based write-only register verification method. According to the UVM based write-only register verification test platform and the verification method, the verification efficiency can be effectively improved, and the verification creditability is improved.

Description

technical field [0001] The invention relates to a write-only register verification test platform based on UVM (Universal Verification Methodology Manual verification methodology). The invention also relates to a write-only register verification method based on UVM verification methodology. Background technique [0002] In chip design, registers are often used to configure chip parameters and control chip functions. According to the specific functions of the chip, the read and write attributes of each register are different. Since some registers with write-only attributes cannot be read through the bus after being written, it is impossible to verify whether the data is written correctly; and the UVM test sequence in the UVM verification methodology is generally placed in a package. It is impossible to see the internal hierarchical structure of the DUT (design under test), that is, the register value cannot be obtained directly through cross-module references; therefore, usin...

AI Technical Summary

Problems solved by technology

Since some registers with write-only attributes cannot be read through the bus after being written, it is impossible to verify whether the data is written correctly; and the UVM test sequence in the UVM verification methodology is generally placed in a package. It is impossible to see the internal hierarchical structure of the DUT (design under test), that is, the register value cannot be obtained directly through cross-module references; therefore, using traditional methods to verify write-only registers, verifiers have to spend a lot of time rewriting the test platform and test sequence

Images