clock circuit for fpga verification platform

Abstract

The invention discloses a clock circuit for an FPGA verification platform, including an FPGA and a 10G PHY chip, and also includes a clock buffer and a clock driver. The circuit recovery clock is divided into two paths through the first clock buffer, and one path passes through the first PLL Converted into clock g and clock h, the other channel is clock d, clock d is converted into the reference clock in the upstream direction of the PON port through the second PLL; clock g is divided into clock r and clock b by the second clock buffer, and clock r is SGMII Clock b is the reference clock of FPGA; clock h is divided into XEXTCLK reference clock and clock s by the third clock buffer, and clock s is the reference clock of XAUI; PON logic clock a, reference clock j of PON port downstream direction , clock w, and the PEXTCLK reference clock are all provided by the clock driver; the clock w is transformed into the reference clock k in the downlink direction of the PON port through the third PLL. The invention significantly reduces the hardware cost and labor cost in technology development, and effectively shortens the development time.

Description

technical field [0001] The invention relates to the field of clock circuits, in particular to a clock circuit used for an FPGA verification platform. Background technique [0002] PON (Passive Optical Network, Passive Optical Network) system is mainly composed of OLT (Optical Line Terminal, Optical Line Terminal), ONU (Optical Network Unit, Optical Network Unit) and ODN (Optical Distribution Network, Optical Distribution Network), usually using point-to- Multipoint tree topology. The most common PON systems are: XG-PON (10-Gigabit-capable Passive Optical Network, 10 Gigabit Ethernet Passive Optical Network) system, 10G EPON (Ethernet Passive Optical Network, Ethernet Passive Optical Network) system and GPON (Gigabit-Capable PON, Gigabit Ethernet Passive Optical Network) system. [0003] For the XG-PON system, the uplink and downlink rate parameters are defined as follows: 9.95328Gbit / s downlink, 2.48832Gbit / s uplink. [0004] For the 10G EPON system, the uplink and downli...

AI Technical Summary

Problems solved by technology

[0009] The technical problem to be solved by the present invention is to solve the problem that due to the different speeds of various PON systems, the required clock frequencies are also different, resulting in high hardware costs and labor costs in technology development, and it takes a long time to develop.

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