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Architecture Design Method of Heterogeneous Multi-core SoC

An architecture, heterogeneous multi-core technology, applied in the field of computer applications, can solve problems such as lack of theoretical methods

Active Publication Date: 2017-12-05
BEIJING SMART LOGIC TECH CO LTD
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, when designers design the SoC architecture of chips, they usually rely on the engineering basis of previous designs and their own experience, but lack a systematic and complete theoretical method to guide the entire design process

Method used

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  • Architecture Design Method of Heterogeneous Multi-core SoC
  • Architecture Design Method of Heterogeneous Multi-core SoC
  • Architecture Design Method of Heterogeneous Multi-core SoC

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Embodiment Construction

[0008] The architecture design method of the heterogeneous multi-core SoC provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0009] figure 1 It is a flowchart of a heterogeneous multi-core SoC architecture design method provided by an embodiment of the present invention.

[0010] refer to figure 1 , in step S101, according to the running time of the function and the number of visits to obtain the first set of calling functions.

[0011] Here, the first call function set is a function with a large amount of computation, a long computation time, or a large number of calls.

[0012] Specifically, use the gprof software of Linux to dynamically analyze the call situation of each function, and determine the function with a large amount of calculation in the program. Referring to the consumption time table of each function shown in Table 1, select the 15 functions that consume the most time among the...

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Abstract

The heterogeneous multi-core SoC architecture design method provided by the present invention includes: obtaining the first call function set according to the running time and access times of the functions in the algorithm of the application field; and designing the simulation input stimulus by analyzing the calculation characteristics of the first call function set ; Determine the exploration space of the first SoC architecture according to the design requirements of the application field; trim the exploration space of the first SoC architecture to obtain the exploration space of the second SoC architecture; randomly select from the exploration space of the second SoC architecture Combining variables, simulating and synthesizing each group of SoC architectures to obtain running time, chip area, and power consumption; using machine learning algorithms to train variable combinations, running time, chip area, and power consumption to obtain regression models or classification models; using The above model explores the exploration space of the second SoC architecture and selects the SoC architecture satisfying multiple constraints from it. The invention can realize optimal heterogeneous multi-core SoC architecture design.

Description

technical field [0001] The invention relates to computer application technology, in particular to an architecture design method of a heterogeneous multi-core SoC. Background technique [0002] With the continuous development of chip manufacturing technology, the problem of energy consumption and heat dissipation makes all the units contained on the chip unable to work normally at the same time, that is, some circuits on the chip will become black silicon (dark silicon), wasting resources. In the past, chips that blindly pursued high frequency, high capacity, and isomorphic multi-core will encounter development bottlenecks; at the same time, the demand for chips with multiple functions, high efficiency, low power consumption, and easy portability in today's society is getting higher and higher, especially the current rapid development. Supercomputing fields, mobile communications and intelligent multimedia fields, etc. As a result, heterogeneous multi-core processor chips fo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/76
Inventor 林忱杜学亮
Owner BEIJING SMART LOGIC TECH CO LTD
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