Multi-bit flip detection method and system

A technology of multi-bit inversion and detection method, which is applied in the field of multi-bit inversion detection methods and systems, can solve the problems of increased false positive rate and insufficient criteria, and achieve sufficient criteria, reduce false positive rate, and improve multi-bit inversion. The effect of detection efficiency

Active Publication Date: 2018-01-02
FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH
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  • Abstract
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  • Claims
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Problems solved by technology

[0004] Based on this, it is necessary to provide a multi-bit flip detection method and system for the problems of high misjudgment rate and insufficient criteria when the above detection method is applied to a highly integrated memory.

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  • Multi-bit flip detection method and system

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Embodiment Construction

[0018] Although the steps in the present invention are arranged with labels, they are not used to limit the order of the steps. Unless the order of the steps is clearly stated or the execution of a certain step requires other steps as a basis, the relative order of the steps can be adjusted.

[0019] see figure 1 , figure 1 is a schematic flowchart of the first embodiment of the multi-bit inversion detection method of the present invention.

[0020] The multi-bit inversion detection method described in this embodiment may include the following steps:

[0021] Step S101, acquiring the physical address of the storage address where the information inversion of the device under test occurs, the inversion information of the storage address, and the reading time of the inversion information, and generating the physical address, inversion information and reading time corresponding to each of the storage addresses. Take time.

[0022] Step S102, judging whether the storage architec...

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Abstract

The present invention relates to a multi-bit inversion detection method and system, the method comprising: obtaining the physical address of the storage address where the information inversion of the device under test occurs, the inversion information of the storage address and the reading time of the inversion information, Generating the physical address, flip information and read time corresponding to each of the storage addresses; judging whether the storage architecture of the device under test is an interleaved architecture; if so, judging the physical address, flip information, and read time corresponding to each of the storage addresses Whether there are at least two storage addresses whose reading time interval is less than the preset time, the physical address interval is less than or equal to the preset address interval, and the inversion information is the same. If there are, there are multiple bit inversions in the detection device. The invention fully considers the influence of the internal storage structure of the device on the multi-bit inversion detection, makes the criterion more sufficient, can be applied to high-integration memory, effectively reduces the misjudgment rate, and improves the multi-bit inversion detection efficiency.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a multi-bit inversion detection method and system. Background technique [0002] For low-integration memories, there are currently many methods for detecting and discriminating multi-bit inversions. Error information can be detected by quantitatively analyzing the detection method of the multi-bit flip contribution of static random access memory (SRAM) in the process: the logical address where the error occurs, the data written into the memory, and the data read from the memory and the time the error occurred. According to the detected error information, after the logical address is converted into a physical address, the visualization images of single event flipping and multi-dimensional flipping can be obtained. Several errors with adjacent physical addresses and the same period of time are judged as multiple bit flips. According to the error rate, device capacity and rea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02
Inventor 张战刚雷志锋岳龙恩云飞
Owner FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH
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