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FPGA (Field Programmable Gate Array) key data protection method for microsatellite

A key data and micro-satellite technology, which is applied in the fields of electrical digital data processing, generation of response errors, instruments, etc., can solve problems such as poor protection capabilities

Inactive Publication Date: 2015-09-23
NORTHWESTERN POLYTECHNICAL UNIV
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Problems solved by technology

[0005] In order to overcome the deficiency that the existing FPGA data protection method has poor protection ability due to error accumulation, the present invention provides a micro-satellite FPGA key data protection method

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specific Embodiment approach

[0033] 3. Key data protection method: Key data protection is based on the first two implementation methods, and the FPGA internal logic of the AHB-Lite host and data detector is designed. The logic design of these two modules is the core content of FPGA key data protection. The specific implementation is as follows:

[0034] a) The AHB-Lite host provides the memory access interface to the data detector, generates and detects error correction codes, and generates multi-bit error interrupts.

[0035] The design method of AHB-Lite mainframe adopts the finite state machine to realize. The logic design is designed according to the control timing of the AHB-Lite bus, and the address signal and control signal are driven on the rising edge of the bus clock to realize the read and write operations of the data by the AHB-Lite host. In order to avoid data read and write conflicts, the write priority is higher than the read priority. First, the state machine is in the "idle" state. Whe...

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Abstract

The invention discloses an FPGA (Field Programmable Gate Array) key data protection method for a microsatellite, and aims to solve the technical problem of poor protection capability due to error accumulation in an existing FPGA data protection method. According to the technical scheme, FPGA resources are partitioned into a local structure, memory resources and an AHB-Lite bus firstly. The memory resources of key data are partitioned into three key memories and one ordinary memory in a way of mounting a slave memory on the AHB-Lite bus. Single-bit data detection and correction and multi-bit data detection are realized in combination with a three-mode redundancy technology and an error correction detection technology. If a single-bit error occurs, data is corrected through an error correction detection function. If a multi-bit error occurs, detection interrupt and a corresponding error data address are generated by the error correction detection function; the memories are re-read with the three-mode redundancy technology; and memory error data is corrected. If single particle upset is detected, the memories are written back, so that device memory data returns to normal.

Description

technical field [0001] The invention relates to an FPGA data protection method, in particular to a micro-satellite FPGA key data protection method. Background technique [0002] Compared with conventional satellites, microsatellites have the characteristics of light weight, low cost, and short design and manufacturing cycle. The widespread use of commercial off-the-shelf (COTS) devices has made microsatellite technology an unprecedented development. The research content of the stability of micro-satellite space electronic equipment is mainly the single event effect protection technology of FPGA. Judging from the test results of several satellites launched by my country, SRAM-type FPGA and DSP single-event flips have caused multiple functional failures of space electronic equipment. From the perspective of the ratio of single event upset (SEU), configuration memory accounts for the largest proportion (research shows that the proportion is sometimes as high as 97%), followed ...

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Application Information

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IPC IPC(8): G06F11/10G06F13/16
Inventor 梅少辉王熠万帅李祎陶晴岳晓奎
Owner NORTHWESTERN POLYTECHNICAL UNIV
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