Single Event Toggle Soft Error Detection Method for FPGA Based on Redundant Interconnection Resources

Abstract

The invention discloses a method for detecting soft errors of FPGA single event flipping based on redundant interconnection resources, which comprises the following steps: Step 1, establishing the connection relationship in FPGA internal interconnection resources; Step 2, not using logic units, directly Insert a comparison circuit into the FPGA device; Step 3, find a copy line for the existing interconnection resources; Step 4, combine the copy line with the comparison circuit to complete the double-backup comparison of the FPGA based on redundant interconnection resources, and realize error detection. The invention develops an efficient search algorithm for redundant interconnection resources by making full use of the phenomenon that there are many redundancy in the interconnection resources in the design, and realizes the high-efficiency online detection of single-event flipping soft errors by means of a simple modification of the FPGA structure. detection.

Description

technical field [0001] The invention relates to the field of FPGA soft error protection and detection, in particular to a FPGA single-event flip soft error detection method based on redundant interconnection resources. Background technique [0002] At present, most FPGA devices use SRAM, that is, static random access memory (Staic Random Access Memory, SRAM) as a storage unit of configuration information. Although SRAM-type FPGA devices have the advantages of short development cycle, low cost, high performance, low power consumption, and reconfiguration, a large number of SRAM configurable cells existing in SRAM-type FPGA devices are easily affected by high-energy particles and cause single-event overturns ( Single Event Update, SEU) soft error, which makes its structure and function change and produces functional failure. With the continuous improvement of device integration and the continuous expansion of FPGA device application scope, the reliability problem caused by si...

AI Technical Summary

Problems solved by technology

[0005] The essence of DWC technology is a detection technology based on hardware redundancy, which needs to provide comprehensive redundancy for various hardware resources such as sequential components, combinational logic, wiring resources, and I / O ports for the circuit, but the comprehensive redundancy strategy will lead to DWC Technology has significant overhead in terms of area, timing, power consumption, and I / O ports

At the same time, the internal resource occupancy rate of FPGA often has a large difference. This kind of unbalanced resource occupancy phenomenon is very common in actual design. Often due to the limitation of certain resources, it cannot realize the complete dual backup comparison technology.

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