Noise-shaping flash successive approximation register analog-to-digital converter (Noise-Shaping Flash-SAR ADC)

Abstract

The invention discloses a noise-shaping flash successive approximation register analog-to-digital converter (Noise-Shaping Flash-SAR ADC), belonging to the field of microelectronics and solid-state electronics. The ADC comprises a front-stage Flash ADC and a rear-stage SAR ADC; the input voltage of the front-stage Flash ADC is obtained by summation of input voltage Vin and a difference value between input of the rear-stage SAR ADC and analog output of the rear-stage SAR ADC; digital output of the front-stage Flash ADC is Dout, 1; the input voltage of the rear-stage SAR ADC is voltage of a difference value between the input of the front-stage Flash ADC and the analog output of the front-stage Flash ADC after passing through a unit delay module; digital output of the rear-stage SAR ADC is Dout, 2; finally a conversion result is obtained by dislocation summation of the Dout, 1 and the Dout, 2. Complexity in design of analog circuits is reduced while establishment of function relationship between G and H (z) is avoided.

Description

technical field [0001] "A parallel successive approximation analog-to-digital converter with noise shaping" (Noise-Shaping Flash Successive Approximation Register Analog-to-Digital Converter, abbreviated as Noise-Shaping Flash-SAR ADC) involves a new type of circuit structure, directly applied The technical field is the design of medium-to-high-speed, medium-to-high-precision analog integrated circuits in the field of microelectronics and solid-state electronics. Background technique [0002] ADCs are generally divided into full parallel analog-to-digital converters (Flash ADC), pipelined analog-to-digital converters (Pipeline ADC), oversampling analog-to-digital converters (ΣΔADC) and successive approximation analog-to-digital converters (SAR ADC). The Figure of Merit (FOM) represents the energy required for each conversion step of the ADC, and is an important indicator to measure the design level of the ADC. figure 1 The generally applicable accuracy-speed ranges of ADCs ...

AI Technical Summary

Problems solved by technology

However, the defect of the Flash-SAR ADC is that the Flash ADC in the Flash-SAR ADC contains a large number of comparators, which increases exponentially with the accuracy, which limits the application of the Flash-SAR ADC in the field of high precision.

In addition, both the pre-stage and the post-stage require a delay module z －0.5 , increasing the complexity of timing

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