Multi-grid transistor and preparation method thereof

Abstract

The invention discloses a multi-grid transistor and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate, a grid oxidation layer, a first polycrystalline silicon layer and a sacrificial oxidation layer; etching the semiconductor substrate to form a through hole; enlarging the size of the through hole formed in the first polycrystalline silicon layer; depositing an isolation oxidation layer on the bottom wall and the side wall of the through hole, wherein the isolation oxidation layer is filled in an enlarged part, which is positioned at the first polycrystalline silicon layer, of the through hole; depositing a second polycrystalline silicon layer in the through hole, so that the second polycrystalline silicon layer forms a second grid structure, and the first polycrystalline silicon layers at two sides of the second polycrystalline silicon layer form a first grid structure and a third grid structure; forming a side wall, a source electrode and a drain electrode at two sides of each of the first grid structure, the second grid structure and the third grid structure. According to the multi-grid transistor, the probability of damaging a fin type structure is avoided, the number of trenches is increased, and the speed of a device is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a multi-gate transistor and a preparation method thereof. Background technique [0002] In the advanced complementary metal oxide semiconductor (CMOS) industry, with the advent of 22nm and smaller dimensions, in order to improve the short channel effect and improve the performance of the device, the Fin Field-effect transistor (Fin Field-effect transistor, FinFET) is formed by Its unique structure is widely used. [0003] FinFET is a metal oxide semiconductor field effect transistor. Its structure is usually formed on a silicon-on-insulator substrate, including narrow and independent silicon strips, as a vertical channel structure, also known as fins, on both sides of the fins There is a gate structure. In general, FinFETs have smaller device structures and better performance. [0004] Such as figure 1 As shown, it is a schematic structural diagram of a FinFET in the p...

AI Technical Summary

Problems solved by technology

For example, under normal circumstances, the fins 13 are very thin, which easily leads to poor stability in the production process, and is prone to abnormalities when subjected to external influences.

For example, vibration and other situations will cause damage to the fins 13. Therefore, how to improve this problem is extremely important.

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