Packaging structure and semiconductor process
A packaging structure and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of increased material cost, reduced mechanical strength of sealant, and uneven distribution
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[0014] refer to figure 1 , shows a schematic cross-sectional view of an embodiment of the packaging structure of the present invention. The packaging structure 10 includes: a first substrate 11 , a second substrate 12 , a chip 13 , several electrical connection elements 14 , at least one spacer element 15 and a sealant 16 . The first substrate 11 has a first surface 111 and a plurality of first conductive contacts 112 , wherein the first conductive contacts 112 are exposed on the first surface 111 of the first substrate 11 . In one embodiment, the first substrate 11 further includes a first solder resist layer (not shown), the first surface 111 of the first substrate 11 is the surface of the first solder resist layer, and is exposed through the opening of the first solder resist layer The first conductive contact 112 . The first conductive contacts 112 can be conductive pads or conductive lines.
[0015] The second substrate 12 has a second surface 121 and a plurality of se...
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