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A Method for Realizing the Synchronization of Multi-channel Analog-to-Digital Converters

An analog-to-digital converter and multi-channel technology, applied in the direction of analog-to-digital converters, etc., can solve the problems of imaging result impact and out-of-synchronization, and achieve phase synchronization, avoid impact, and avoid glitches

Active Publication Date: 2017-12-22
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For multi-channel high-speed ADCs, or using multiple single-channel high-speed ADCs at the same time, the phases between the channels may not be synchronized after the ADC configuration is completed, which will have a great impact on the imaging results

Method used

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with accompanying drawing:

[0020] combine figure 1 , is a schematic diagram of a hardware implementation structure of a method for realizing synchronization of multi-channel analog-to-digital converters of the present invention. In the embodiment of the present invention, the FPGA chip is electrically connected to the configuration interface of the multi-channel analog-to-digital converter (multi-channel high-speed ADC), and is used to configure the working mode of the multi-channel analog-to-digital converter, so that it is in the multi-channel test mode and normal working mode or other modes. For example, the configuration interface is an SPI interface. The number of channels of the multi-channel analog-to-digital converter is expressed as N, and for the N channels of the channel number of the multi-channel analog-to-digital converter (corresponding to figure 1 Each channel is electrically conne...

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Abstract

The invention belongs to the technical field of radar radio frequency signal acquisition, and discloses a method for realizing the synchronization of multi-channel analog-to-digital converters. It includes the following steps: configuring the multi-channel analog-to-digital converter to work in a multi-channel test mode; the multi-channel analog-to-digital converter generates a data differential pair and an associated clock differential pair, and converts the data differential pair and the associated clock differential pair of each channel Send it to the FPGA chip; the FPGA chip obtains the corresponding single-ended clock signal and single-ended data signal; configure the corresponding delay value for each data bit of the single-ended data signal of each channel, according to the single-ended data signal of each channel Each data bit is configured with a corresponding delay value, and the signal of each data bit of the single-ended data signal of each channel is delayed; the single-ended data signal of each channel after the delay processing is serial-to-parallel converted to obtain The corresponding parallel data; according to the phase relationship between the parallel data of each channel, the parallel data of each channel is phase-aligned.

Description

technical field [0001] The invention belongs to the technical field of radar radio frequency signal acquisition, in particular to a method for realizing the synchronization of multi-channel analog-to-digital converters, which is mainly used for the analog-to-digital conversion of radar radio frequency signals. Background technique [0002] Due to the advantages of radar itself (all-weather, no environmental requirements, etc.), radar imaging technology has received extensive attention and research. Radar imaging technology can be applied in complex conditions such as dark nights and rainy days, making up for many shortcomings of optical imaging. [0003] As the first step of radar imaging technology, the acquisition of radar signal plays a vital role in the whole imaging work. The quality of the collected radar echo signal directly determines the quality of the final imaging result. Higher resolution and higher quality require higher sampling accuracy, faster sampling speed...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/12
Inventor 朱圣棋全英汇王金龙李亚超崔俊鹏姚鑫东徐瑞
Owner XIDIAN UNIV
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