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Folding and interpolating analog-digital converter employing offset averaging and interpolation shared resistance network

An analog-to-digital converter and offset averaging technology, applied in the direction of analog-to-digital converters, can solve the problems of increasing the power consumption of the analog-to-digital converter, which is not conducive to the low power consumption and high energy efficiency design of the folding and interpolating analog-to-digital converter structure , to simplify the design of cascaded bandwidth and facilitate the design of high bandwidth and high energy efficiency

Active Publication Date: 2015-02-04
FUDAN UNIV
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Problems solved by technology

This interpolation method will also increase the power consumption of the ADC, which is not conducive to the low power consumption and high energy efficiency design of the folding interpolation ADC structure.

Method used

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  • Folding and interpolating analog-digital converter employing offset averaging and interpolation shared resistance network
  • Folding and interpolating analog-digital converter employing offset averaging and interpolation shared resistance network
  • Folding and interpolating analog-digital converter employing offset averaging and interpolation shared resistance network

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Embodiment Construction

[0024] The offset averaging and interpolation shared resistor network structure proposed by the present invention and the high bandwidth, low power consumption folded interpolation analog-to-digital converter structure using this technology will be described in detail below in conjunction with the accompanying drawings.

[0025] Offset averaging and interpolation shared resistor network structures such as Figure 6 As shown, the structure consists of: splitting the offset average resistance R a 55. A folder input differential pair 56, 57, 59, and a folder resistive load 60, an i-th stage folder 58, and an i+1-th stage folder 61 are formed. In this structure the original offset average resistance R A Split into two equal R's a , so as to realize the 2 times interpolation operation to generate the interpolation signal F P_C and F N_C , initial signal F P_A and F N_A and F P_B and F N_B output directly. After adopting this technology, the offset average resistor and the ...

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Abstract

The invention relates to the technical field of the integrated circuits and specifically relates to a folding and interpolating analog-digital converter employing an offset averaging and interpolation shared resistance network. The folding and interpolating analog-digital converter is composed of a single T / H circuit, a reference resistor string, a pre-amplifying circuit array, an offset averaging and interpolation shared resistance network (having the interpolation coefficient of 1), a folding circuit (levels 1-N) having the folding coefficient of F, a comparator array, a digital coding circuit and a binary digit code output drive motor, wherein interpolation is performed in a passive resistance mode, and passive interpolation resistance and offset averaging resistance are shared and fused. The folding and interpolating analog-digital converter employing the offset averaging and interpolation shared resistance network has the advantages that the influence of the passive interpolation resistance on the offset averaging resistance when the offset averaging resistance is cascaded with the passive interpolation resistance, other independent interpolation circuit modules in a traditional structure are omitted and the power consumption is reduced, the cascade bandwidth in a folding and interpolating signal path can be designed smoothly and the design of system high bandwidth can be realized more easily.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a foldable interpolation analog-digital converter with high bandwidth and low power consumption that adopts offset averaging and interpolation shared resistance network. Background technique [0002] The traditional folded interpolation analog-to-digital converter structure such as figure 1 As shown, it is mainly composed of a single tracking and holding circuit 1, a reference voltage resistor string 2, a pre-amplifier circuit array 3, an offset average resistor network 4 at the output end of the pre-amplifier, and folding circuit stages 5, 8, 11, and N with N-level folding coefficients of F Level interpolation coefficient is the interpolation circuit level 6,9,12 of 1, each level interpolation circuit level output terminal offset average resistance network 7,10,13, comparator array circuit module 14, digital encoding circuit module 15 and binary digit Co...

Claims

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Application Information

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IPC IPC(8): H03M1/12
Inventor 任俊彦王明硕陈勇臻刘文娟冯泽民叶凡许俊李宁
Owner FUDAN UNIV
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