Cache managing method and device

Abstract

The invention discloses a cache managing method and device. The method is applied to a process of realizing an AFDX (Avionics Full Duplex Switched Ethernet) communication protocol by an FPGA (Field Programmable Gate Array). Under a scene of an FPGA managing storage, the method comprises the following steps: confirming a starting address and an ending address of a continuous address section used by a storage; slicing the storage within the scope of the starting address and the ending address according to the length of a predefined memory sheet, thereby acquiring the memory sheet; storing a first address of the memory sheet acquired by slicing; after receiving a distribution applying signal sent by a memory request party, inquiring if a usable memory sheet exists; if yes, distributing the memory sheet to the memory request party according to the size of the memory requested by the memory request party and sending the first address of the distributed memory sheet to the memory request party. According to the invention, the effective distribution and releasing of the cache during the realizing process of the FPGA of the AFDX communication protocol are realized.

Description

technical field [0001] The invention relates to the realization of an avionics full-duplex real-time Ethernet communication protocol, in particular to a cache management method and device. Background technique [0002] AFDX (Avionics Full Duplex Switched Ethernet, Avionics Full Duplex Switched Ethernet) is a technology implemented by Airbus for certain aircraft data networks (Aircraft Data Networks) according to the ARINC664 specification. At present, it has been widely used to interconnect electronic systems in aviation vehicles, such as engines, flight control components, cruise systems, etc. To date, AFDX has been used in the A380, A400M and Boeing B787 programs. [0003] In the implementation process of the protocol, a large-capacity memory is required to cache data packets, so the storage space of the large-capacity memory needs to be managed. If FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is used for memory There is currently no suitable way f...

AI Technical Summary

Problems solved by technology

[0003] In the implementation process of the protocol, a large-capacity memory is required to cache data packets, so the storage space of the large-capacity memory needs to be managed. If FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is used for memory management, currently there is no suitable way, or it is not suitable for data cache management in the process of AFDX protocol implementation

Images