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FPGA-based IRIG-B code decoder and decoding method thereof

A decoder and B code technology, applied in FPGA-based IRIG-B code decoder and its decoding field, can solve the problems of affecting micro-processing response and taking up a large processing time, so as to improve efficiency and pertinence, reduce noise, Effect of improving precision of judgment

Active Publication Date: 2014-10-15
CHINA XD ELECTRIC CO LTD
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Problems solved by technology

[0003] In the prior art, the decoder for the IRIG-B code is implemented by a microprocessor, and the analysis of the IRIG-B code will take a large amount of processing time due to the sequential execution limitation of the microprocessor, which will directly affect the performance of the microprocessor on other tasks. response

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  • FPGA-based IRIG-B code decoder and decoding method thereof
  • FPGA-based IRIG-B code decoder and decoding method thereof

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Embodiment Construction

[0029] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0030] A kind of FPGA-based IRIG-B code decoder of the present invention, as figure 1 As shown, it includes a B code analysis unit and an information output unit arranged in the FPGA; the B code analysis unit includes a symbol identification module, an information extraction module and a format conversion module connected in sequence, and the information output unit includes a UTC time module connected in sequence and interface module; the code element identification module is used to process the IRIG-B code signal of external input; the information extraction module is used to receive the code element type output by the symbol identification module, and provides the punctual reference point signal to the UTC time module; the format conversion module It is used to provide the UTC second signa...

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Abstract

The invention provides an FPGA-based IRIG-B code decoder and decoding method thereof. The decoder includes a B code analysis unit and an information output unit which are arranged in an FPGA; the B code analysis unit comprises a code element recognition module, an information extraction module and a format conversion module which are connected with one another sequentially; the information output unit comprises a UTC time module and an interface module which are connected with each other sequentially; the code element recognition module is used for processing IRIG-B code signals inputted from the outside; the information extraction module is used for receiving code element types outputted by the code element recognition module, and providing on-time reference point signals for the UTC time module; the format conversion module is used for providing UTC second signals to the UTC time module; and the information output unit provides PPS and UTC time signals for external applications through the interface module. The method comprises the following steps of: 1) code element analysis; 2) information extraction; 3) UTC second signal calculation; and 4) UTC time synthetic output.

Description

technical field [0001] The invention relates to a time synchronization technology in a power system, in particular to an FPGA-based IRIG-B code decoder and a decoding method thereof. Background technique [0002] With the rapid development of the power system, the requirement for time synchronization is increasingly urgent, and an accurate, safe and reliable clock source is needed to provide an accurate time reference for various operating equipment in the power system. Since the Global Positioning System (GPS) has become a global sharing and extremely high-precision time release system, GPS-based time synchronization signals have been widely used in power systems. The methods of GPS time synchronization signal mainly include pulse synchronization method, serial port information synchronization method, IRIG-B code synchronization method, etc. The IRIG-B code synchronization method is accurate in time synchronization and simplifies the time synchronization circuit. - The B c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G04R20/00
Inventor 白世军石楠陈凯金猛
Owner CHINA XD ELECTRIC CO LTD
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