Semiconductor chips and semiconductor devices

Abstract

Provided are a semiconductor chip and a semiconductor device that improve wiring properties in a substrate on which a semiconductor chip is flip-chip mounted. In the flip-chip mounted semiconductor chip, the inner die pad row and the outer die pad row arranged in a zigzag shape inside and outside the IO cell are arranged at a predetermined interval or more. The predetermined interval is an interval at which one via hole can be disposed between the inner and outer substrate pad rows on the substrate that are connected face-to-face with the inner and outer chip pad rows. Alternatively, the predetermined interval means an interval at which an opening for wiring a solder resist layer to which a plated line is to be back-etched later can be formed at the interval. Even when there is no space for forming wiring between the outer substrate pad columns, the wiring property of the substrate can be improved.

Description

technical field [0001] The present invention relates to a semiconductor chip flip-chip mounted on a substrate and a semiconductor device mounted thereon, and is particularly applicable to improving the wiring properties of the mounted substrate. Background technique [0002] In flip-chip mounting, on a substrate on which a semiconductor chip is mounted, pads to be connected are provided at positions facing the pads of the semiconductor chip, and are connected to each other via bumps or the like to achieve electrical conduction. Hereinafter, pads provided on a substrate for connection to a semiconductor chip are referred to as substrate pads, and pads on the semiconductor chip are simply referred to as pads or die pads. [0003] In semiconductor chips, especially with the increase in the integration level of large-scale LSI (Large Scale Integrated circuit, large-scale integrated circuit) such as SoC (System on Chip), there is a need for more electrodes, that is, the number of...

AI Technical Summary

Problems solved by technology

For example, the via hole cannot be placed near the substrate pad to be connected to it, and the lead-out of the wiring from the substrate pad to the via hole increases, the wiring impedance increases, and the electrical characteristics deteriorate.

In addition, the wiring performance on the layout surface is reduced, the area of ​​the substrate is increased, and, for example, when the substrate is a mounting substrate of an LSI package, there are problems such as an increase in the size of the package that can be accommodated.

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