On-chip communication method and on-chip communication device on basis of three physical interconnection lines for integrated circuits

Abstract

The invention discloses an on-chip communication method on the basis of three physical interconnection lines for integrated circuits. The on-chip communication method includes preliminarily connecting a master with slaves by clock lines and data lines, cascading acknowledgment lines of the various slaves step by step by the aid of AND logics and finally connecting the acknowledgment lines with an acknowledgment interface of the master; segmenting each message into five micro-packets including a start bit, a message header, an address, a data volume and a stop bit when the message is transmitted from the master to the corresponding slave, sequentially transmitting each five corresponding micro-packets including the start bit, the message header, the address, the data volume and the stop bit between the master and the corresponding slave, enabling the slaves to receive the messages comprising the multiple micro-packets from the master via the clock lines and the data lines in transmission procedures, enabling the slaves to transmit acknowledgment and message read return data to the master via the acknowledgment lines, and enabling the slaves to receive message write data via the data lines. The message write data are transmitted from the master. The on-chip communication method has the advantages of few interconnection lines and occupied hardware resources and capability of supporting flexible slave power shut-off strategies.

Description

technical field [0001] The invention relates to the on-chip communication field of an integrated circuit SOC chip, in particular to an integrated circuit on-chip communication method and device based on three physical interconnection lines. Background technique [0002] SOC chip design has become the mainstream in the field of chip design, especially in the field of embedded mobile communication. Generally, many components are integrated on the SOC chip, such as SDRAM controller, USB, PCIE, SATA, UART, SPI, SIM card controller and other functional components, often reaching dozens of types. In order to connect many functional components together, people have studied a variety of SOC on-chip bus structures, such as AMBA, CoreConnect, etc. These buses are all synchronous bus types, which have the advantages of high bandwidth and low delay, but require the devices on the bus to belong to The same clock domain or cross-clock conversion, and this type of bus requires more interc...

AI Technical Summary

Problems solved by technology

However, when multiple slave devices are cascaded, the address bus and data bus structure of the master device and each slave device must be arranged separately, and the number of interconnection lines is large, so the increase in the number of slave devices will inevitably lead to time-consuming physical implementation. Occupies a large number of routing resources, increasing the difficulty of timing constraints during physical implementation

Moreover, the DCR bus structure cannot support low-power technologies such as power-off. Once a node in the cascaded node is powered off, all accesses to its subsequent nodes will not be possible.

[0004] To sum up, the daisy chain DCR bus has the following problems: (1) The address, data, control and other signals of the DCR bus have separate physical connection lines, resulting in many physical connections of the entire DCR bus, occupying a large amount of wiring resources, increased chip area

Moreover, there is a timing relationship between each group of interconnect lines, which must be constrained in the physical design, which increases the difficulty and complexity of the physical design; (2) On the slave device chain of the DCR bus, a slave device that is powered off will cause All subsequent slave devices are inaccessible, so low-power management technologies such as flexible device power-off are not supported

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