Parasitic extraction in an integrated circuit with multi-patterning requirements

Abstract

Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form.

Description

technical field [0001] The present invention relates to systems and methods for integrated circuit ("IC") fabrication and optimization, and more particularly to methods for extracting parasitics in the design of integrated circuits with multi-patterning requirements. systems and methods. Background technique [0002] An IC is a device (eg, a semiconductor device) or electronic system that includes many electronic components such as transistors, resistors, diodes, and the like. These components are often interconnected to form multiple circuit components such as gates, cells, memory units, arithmetic units, controllers, decoders, and the like. An IC includes multiple wiring layers that interconnect its electronic and circuit components. [0003] Design engineers design ICs by transforming a logical or circuit description of the IC's components into a geometric description called the design layout. An IC design layout typically includes circuit blocks with pins (eg, a geome...

AI Technical Summary

Problems solved by technology

However, splitting the layers into multiple masks can cause timing variations due to mask misalignment during fabrication

For example, misalignment of layout masks can lead to variations in coupling capacitance between polygons on different masks, which in turn affects both the net's total capacitance and coupling

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