Test pad sharing circuit

Abstract

The invention discloses a test pad sharing circuit. The circuit comprises a test pad and a control circuit. The control circuit is used for connecting the test pad, a negative-voltage circuit, a positive high-voltage circuit and a positive low-voltage circuit so as to control the test pad to carry out input or output testing on the negative-voltage circuit, the positive high-voltage circuit and the positive low-voltage circuit respectively according to the testing purposes. A small number of MOS tubes are added, the area is not increased much, but the number of testing pads is effectively reduced, and accordingly the area waste of a chip is effectively reduced.

Description

technical field [0001] The present invention relates to a test pad sharing circuit, in particular to a test pad sharing circuit that enables the test pad to test multiple circuits. Background technique [0002] At present, integrated circuits are becoming more and more complex, their functions are becoming more and more powerful, and the manufacturing process is becoming more and more advanced. The typical process line width is only 0.18um, 0.13um, 90nm, 45nm or even narrower. In order to ensure the normal operation of each circuit, In addition to testing on the normal pins outside the bare chip (Die), some test pads are usually placed at some key points to facilitate problem tracking when problems occur. As the complexity of integrated circuits increases, more and more points need to be placed on the tracking pads, because the test pads generally have a large area such as 60×60um, and it is generally not suitable to place circuits on the top and bottom, so placing more test...

AI Technical Summary

Problems solved by technology

Although this structure allows one test pad to test two circuits, it is still not efficient and wastes chip area

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