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A high-speed data extraction method based on fpga-based input and output sequence arrangement

An input-output, high-speed data technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as limitations of extraction conditions

Active Publication Date: 2016-10-05
CHINA ELECTRONIS TECH INSTR CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The extraction ratio achieved by such an extraction operation is a multiple of 4, and the extraction situation is limited

Method used

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  • A high-speed data extraction method based on fpga-based input and output sequence arrangement
  • A high-speed data extraction method based on fpga-based input and output sequence arrangement

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Experimental program
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Embodiment 1

[0033] The present invention extracts 12 sets of data input each time, and solves the problem in two cases during design, one is the case that the extraction ratio is less than 12, and the other is the case that the extraction ratio is greater than or equal to 12. For the case where the extraction ratio is less than 12, because multiple values ​​may be extracted in one input, each extraction ratio is processed separately according to the different extraction ratios. For the case where the extraction ratio is greater than or equal to 12, there is at most one extraction value for each input, which can be realized by performing a loop algorithm. The extraction method can realize arbitrary extraction ratio extraction of high-speed A / D sampling data.

[0034] The input and output data of this method are 12 groups of data groups arranged in a certain order, and the order and definition of the fields of the input and output data groups are as follows:

[0035] The input is defined a...

Embodiment 2

[0086] On the basis of above-mentioned embodiment, further as Figure 1 to Figure 2 As shown, a high-speed data extraction method based on an FPGA-based input and output sequence arrangement, including the following steps:

[0087] Step 1: Input 12 sets of data; judge whether the extraction ratio is less than 12, if yes, go to step 6, otherwise go to step 2;

[0088] Step 2: Determine whether the count value meets the pumping condition, if yes, go to step 3, otherwise, return to step 1 after counting up by 12;

[0089] Step 3: Position and extract one of the 12 sets of data in step 1 as the extracted value, enter step 4, count the remainder into the next cycle and return to step 1;

[0090] Step 4: assign the extracted value to the output number in sequence; go to step 5;

[0091] Step 5: Judging whether the 12 sets of data output conditions are met, if yes, output the value of the 12 sets of data extracted, and after the output count is cleared, return to step 4; otherwise,...

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Abstract

The invention provides a high-speed data extracting method achieving input and output arranged in sequence based on an FPGA. Direct extraction at a certain extraction ratio is carried out on GHz and higher high-speed original sampling data in the FPGA, the method requires that input data are a set of high-speed A / D collection data fields arranged in sequence, and output extraction data sets are achieved in output, wherein the output extraction data sets are identical with the input data in sequence and width, and the speed of the output extraction data sets is reduced to the fraction of the extraction ratio. The high-speed data extracting method achieving the input and output arranged in sequence based on the FPGA is mainly applied to the situation that a high-speed sampling system carries out extraction on the high-speed A / D original sampling data, the sequence of SRAM storage carried out on the high-speed sampling data is not disorganized due to the fact that the input data and the output data are identical in sequence arranging mode, convenience is brought for the SRAM data storage and subsequent digital signal processing and analysis, data extraction is carried out according to the certain extraction ratio, and the data speed is made to be reduced to the fraction of the original speed. Through the utilization of the scheme, the problems of the random extraction ratio and the extraction mobility of the data direct extraction in multi-path output of a high-speed converter are solved successfully, and extraction modes are flexible.

Description

technical field [0001] The invention belongs to the technical field of data extraction, and in particular relates to a high-speed data extraction method based on an FPGA-based input and output sequence arrangement. Background technique [0002] Data extraction and data extraction of the original data sequence in a certain way are applied in many real cases. The general extraction method is to extract values ​​sequentially. For example, the time function of an original data model is X(t ), (t takes 0, 1, 2...infinity), the operation of taking one value for every N values ​​is performed on the model function, and the extraction operation of the extraction ratio of N is performed on the model. The same is true for the application method and principle of the extraction method in the sampling system, and the extraction behavior of the data sampled by the sampling system according to time at a certain interval can effectively reduce the data rate. [0003] Based on the current hi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/30
CPCG06F16/254
Inventor 白月胜邵利艳
Owner CHINA ELECTRONIS TECH INSTR CO LTD
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