Method for Improving Write Redundancy of SRAM

A static random, write redundancy technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of small equivalent resistance, small write redundancy, etc., to increase the equivalent resistance , the effect of reducing the turn-on current and increasing the parasitic resistance

Active Publication Date: 2016-03-23
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the existing SRAM, the equivalent resistance of the pull-up transistor is small, which in turn leads to a small write margin (WriteMargin) of the SRAM

Method used

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  • Method for Improving Write Redundancy of SRAM
  • Method for Improving Write Redundancy of SRAM
  • Method for Improving Write Redundancy of SRAM

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Embodiment Construction

[0017] In order to illustrate the technical content, structural features, achieved goals and effects of the present invention in detail, the following will be described in detail in conjunction with the embodiments and accompanying drawings.

[0018] see figure 1 , figure 1 Shown is a schematic diagram of an equivalent circuit for writing in the SRAM of the present invention. Write margin (WriteMargin) is an important parameter to measure the write performance of the SRAM unit. In the writing equivalent circuit of the SRAM, it is assumed that the first node 1 stores data at a low potential (that is, the stored data is "0"), and the second node 2 stores data at a high potential (that is, stores The data is "1"), non-limiting list, for example, writing a high potential to the first node 1, writing a low potential to the second node 2, before the writing action, the first bit line 3 will be precharged to a high potential, and the second bit line 4 will be precharged to a low p...

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Abstract

A method for improving the write redundancy of SRAM, comprising: step S1: before the polysilicon gate etching process, perform Group V elements on the gate of the NMOS device of the control transistor and the gate of the NMOS device of the pull-down transistor Pre-implantation; step S2: pre-implantation of Group V elements on the gate of the PMOS device of the pull-up transistor. In the present invention, the gate of the NMOS device is pre-implanted with Group V elements to adjust the threshold voltage of the CMOS device and the turn-on current; the gate of the PMOS device of the pull-up transistor is pre-implanted with Group V elements, so that the The relative doping concentration of the polysilicon gate is reduced, thereby increasing the parasitic resistance of the polysilicon gate and the depletion phenomenon of the polysilicon gate, resulting in a decrease in the turn-on current of the pull-up transistor, thereby increasing the pull-up transistor during the writing process of the SRAM. The equivalent resistance reduces the potential of the second node and improves the writing redundancy of the SRAM.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for improving the writing redundancy of a static random access memory. Background technique [0002] Static Random Access Memory (SRAM), as an important product in semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. [0003] Generally, the layout of the SRAM below 90nm includes three levels of active area, polysilicon gate, and contact holes, and control transistors are respectively formed on the layout area, and the control transistors are NMOS devices; pull-down transistors (PullDownMOS), the pull-down transistor is an NMOS device; the pull-up transistor (PullUpMOS), the pull-up transistor is a PMOS device. However, in the existing SRAM, the equivalent resistance of the pull-up transistor is small, which leads to a small write margin (WriteMargin) of the SRAM. Seeking a method for in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8244H01L21/28
CPCH01L29/49H01L21/28008H10B10/12
Inventor 俞柳江
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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