Space management data generation method oriented to integrated circuit interconnection capacitance parameter extraction

Abstract

The invention provides a space management data generation method oriented to integrated circuit interconnection capacitance parameter extraction. The method includes the following steps: initializing a root node of an octree of an integrated-circuit three-dimensional simulation space; retaking a conductor B from an integrated circuit interconnection structure; starting from the root node, performing depth-first traversal on the octree; acquiring a next traversed node T corresponding to a three-dimensional unit T in the integrated-circuit three-dimensional simulation space; when the node T is a leaf node, judging whether the conductor B should be inserted into a candidate conductor list of the three-dimensional unit T or not according to a preset minimum distance threshold L(T); updating the minimum distance threshold L(T). After all the conductors are inserted into the candidate conductor list, space management data required for the integrated circuit interconnection capacitance parameter extraction are acquired. By the method, generation time for the space management data can be shortened greatly, so that capacitance parameter extraction can be performed on the large-scale integrated circuit interconnection structure.

Description

technical field [0001] The invention relates to the field of physical design of VLSI (Very Large Scale Integrated circuits, VLSI), in particular to the extraction of capacitance parameters of integrated circuit interconnections. Background technique [0002] In the design process of integrated circuits, the functional description must first be proposed, and then the layout describing the size and structure of the semiconductor process is obtained through logic design and layout design, and finally layout verification is performed, that is, computer software simulation is used to verify whether the above design meets the requirements. If the requirements are met, proceed to the next step of manufacturing. Otherwise, if the requirements are not met, return to logic design and layout design for necessary corrections. In layout verification, an important link is "interconnection parasitic parameter extraction". [0003] With the development of integrated circuit manufacturing ...

AI Technical Summary

Problems solved by technology

However, this generation method is inefficient to run, especially when dealing with large-scale interconnect structures, and the running time is too long

Images