Accelerating core virtual scratch pad memory method based on heterogeneous multi-core platform

Abstract

The invention discloses an accelerating core virtual scratch pad memory method based on a heterogeneous multi-core platform. The accelerating core virtual scratch pad memory method includes the following steps: (1) dividing shared L2Cache into two portions of common L2Cache and a virtual scratch pad memory (SPM) logically; (2) setting a virtual SPM access interface; (3) setting a replacing strategy of the common L2Cache and the virtual SPM again; (4) addressing the virtual SPM and a memory uniformly; and (5) defining a virtual SPM space request and a released MIPS assembling command. By optimizing a storage cache sub-system of the heterogeneous multi-core platform partially, data interaction between a general processing core and an accelerating core is no longer finished through the memory and is finished by achieving data sharing in the virtual SPM. By means of the method, shared data interaction speed between the general processing core and the accelerating core is increased effectively, and the integral performance of the heterogeneous multi-core platform is obviously improved. Meanwhile, the virtual SPM can replace an SPM of the accelerating core partially, the capacity of the SPM of the accelerating core itself can be saved, and the cost of hardware is reduced.

Description

technical field [0001] The invention belongs to the field of memory access optimization for heterogeneous multi-core platforms of computer architecture, and specifically relates to a method for accelerating core virtual note memory based on heterogeneous multi-core platforms. Background technique [0002] In recent decades, with the development of semiconductor technology and the demand for high-performance computing, computer architecture has developed rapidly. The development of semiconductor technology follows Moore's Law, and the number of transistors integrated on the processor chip continues to break through. The chip manufacturing process has developed from 10μm in 1971 to the current 22nm. It is expected that in 2014, Intel will launch a processor chip with a 14nm process. Processor architecture has experienced the evolution from single-core to multi-core, from simple to complex. [0003] The number of general-purpose cores integrated on the current mainstream mul...

AI Technical Summary

Problems solved by technology

However, this will bring new problems: the shared data interaction between the general processing core and the acceleration core on the heterogeneous multi-core platform requires multiple copies of the data, which will involve multiple memory accesses. For SPM, the access speed is very slow, which seriously slows down the overall running speed

In addition, the bandwidth of the data bus between the general-purpose processing core and the acceleration core is limited, and a large amount of data transmission also has a large delay, which also affects the overall performance of the heterogeneous multi-core platform to a certain extent.

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