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Optimization method of addition chain and integrated circuit adopting addition chain

An optimization method and technology of adding chain, applied in the field of FPGA, can solve the problems of insufficient input terminal utilization and inflexible design, and achieve the effects of delay change, resource reduction, and area utilization improvement.

Inactive Publication Date: 2013-08-21
CAPITAL MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in figure 1 In the summing chain unit shown, only two inputs of the LUT 106 are actually used, and the input terminals are not fully utilized
In addition, the carry LUT is fixed after the macro mapping, which will also lead to inflexibility in design

Method used

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  • Optimization method of addition chain and integrated circuit adopting addition chain
  • Optimization method of addition chain and integrated circuit adopting addition chain
  • Optimization method of addition chain and integrated circuit adopting addition chain

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Embodiment Construction

[0016] According to the embodiment of the present invention, whether there is other logic before the LUT can be checked in the mapped netlist, and the existing logic is absorbed into the LUT. Thus, the utilization rate of the input resource of the LUT is increased, and the area utilization rate is also improved.

[0017] figure 2 The optimization method of the first embodiment of the present invention is illustrated. like figure 2 As shown in the upper part of , the addition chain includes a look-up table LUT 206, an exclusive OR gate XOR 104 and a multiplexer MUX102. figure 2 Exclusive OR gate XOR 104 and multiplexer MUX 102 in figure 1 XOR gates and multiplexers in have basically the same function. figure 2 The addition chain in the upper half is different from figure 1 The difference lies in the imaginary box on the left, in addition to the LUT 206, there is an exclusive OR gate 208 in the imaginary box.

[0018] The LUT 206 has two signal input terminals for rece...

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Abstract

The invention provides an optimization method of an addition chain and the addition chain after optimization. The optimization method comprises the following steps of conducting lookup on a logic circuit before at least one input end of a lookup table in a netlist after the addition chain is reflected, wherein the addition chain comprises the lookup table, an exclusive-or gate and a multi-channel selector; sharing an input signal by a first input end of the lookup table and one input end of the multi-channel selector; absorbing the logic circuit in the lookup table. According to the optimization method, the area utilization rate is improved, the number of resources is reduced, and delay is changed.

Description

technical field [0001] The invention relates to the FPGA field, in particular to an optimization method for an addition / subtraction chain. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array, has the characteristics of allowing multiple programming and fast finished products, so it is more and more widely used. [0003] FPGA can realize the logic function function through the look-up table. A generic type of lookup table is used to implement any function that can be defined between the input and output of the lookup table. Larger functions can be broken down into smaller functions that fit into the LUT. Of course, FPGAs require other types of gates in addition to look-up tables. Since each function is implemented independently, there is often redundancy in the gate circuits used between adjacent functions. [0004] figure 1 is a schematic diagram of a prior art addition chain. like figure 1 As shown, the addition ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/02
Inventor 樊平耿嘉
Owner CAPITAL MICROELECTRONICS
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