Rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in near field communication

A technology of LDPC code and serial encoder, which is applied in the field of channel coding, can solve problems such as high cost, large registers, and high power consumption of the circuit, and achieve the effects of simple structure, reduced registers, and reduced power consumption

Inactive Publication Date: 2013-08-07
RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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Problems solved by technology

One of the disadvantages of this scheme is that a large number of registers are required, which will inevitably lead to large power consumption and high cost of the circuit.

Method used

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  • Rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in near field communication
  • Rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in near field communication
  • Rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in near field communication

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Embodiment Construction

[0020] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0021] Since the generator polynomial g of the circulant matrix i,j Rotating right n bits is equivalent to rotating it left b-n bits, ie Then equation (3) can be rewritten as

[0022] s i G i , j = e i × b g i , j l ( b ) + e i...

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Abstract

The invention provides a rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in near field communication. The encoder comprises 2 generating polynomial lookup tables which prestore cyclic matrix generating polynomials of the generating matrixes, 2 511-bit binary multipliers which perform scalar multiplication on information bit and the generating polynomials, 2 511-bit binary adders which perform modulo 2 addition on products and contents of shift registers, and 2 511-bit shift registers which store the sums which are rotated left for one bit. Finally, calibration data are contained in the 2 shift registers. The serial encoder provided by the invention is applicable to a near field communication system of consultative committee for space data systems (CCSDS), and has the advantages of few registers, simple structure, low power consumption, low cost and the like.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to a serial coder of a quasi-cyclic LDPC code in a CCSDS near-earth communication system. Background technique [0002] Low-Density Parity-Check (LDPC) code is one of the efficient channel coding techniques, and quasi-cyclic LDPC (Quasic-LDPC, QC-LDPC) code is a special LDPC code. Both the generation matrix G and the check matrix H of the QC-LDPC code are arrays composed of cyclic matrices, which have the characteristics of segmental circulation, so they are called quasi-cyclic LDPC codes. The first row of the circulant matrix is ​​the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the previous row by 1 bit. Therefore, the circulant matrix is ​​completely characterized by its first row. Usually, the first row of a circulant matrix is ​​called its generator polynomial. [0003] The CCSDS near-earth communic...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 张鹏刘志文张燕
Owner RONGCHENG DINGTONG ELECTRONICS INFORMATION SCI & TECH CO LTD
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