CLB-bus-based NorFLASH memory interface chip with high utilization ratio

Abstract

The invention provides a CLB-bus-based NorFLASH memory interface chip with high utilization ratio. The memory interface chip comprises a CPU processor, a CLB bus, a NorFlash interface unit and a NorFlash memory, wherein the NorFlash memory communicates with the CPU processor through the NorFlash interface unit by the CLB bus; the NorFlash interface unit further comprises a power-on detection circuit, an address decoding circuit, a bad block replacement circuit and a writing control circuit, as well as a configuration register set and a state register set; an information block is arranged in the NorFlash memory and records the addresses and the number of bad blocks in the NorFlash memory and the bad block replacement function enabling information of a replacement unit; a bad block register used for storing information from the information block is arranged in the power-on detection circuit; and the bad block replacement circuit is used for re-mapping the addresses of the bad blocks. The NorFLASH memory interface chip improves the NorFLASH utilization ratio to a greater extent.

Description

technical field [0001] The invention relates to a NorFLASH storage interface chip, in particular to a high-utilization NorFLASH storage interface chip based on a CLB bus. Background technique [0002] NorFLASH can run code directly on the chip, with excellent stability and high transmission rate, which is very suitable for embedded systems as NorFLASH ROM. At present, NorFLASH has been widely used in SOC chips (System on Chip, called system-on-chip, also known as system-on-chip). Appropriate interface design is crucial to the application of NorFLASH on SOC chips. When reading and writing NorFLASH operations, it is necessary to control many control signals on it. If the NorFLASH control signals are directly implemented by register control, it will consume a lot of CPU resources, and the operation steps are cumbersome. It takes a lot of software resources to operate and replace the steps, and the software maintenance is more complicated. Therefore, how to provide a NorFLASH...

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Problems solved by technology

[0003] The object of the present invention is to provide a high-utilization NorFLASH storage interface chip based on the CLB bus, which can improve the utilization of NorFLASH to a greater extent; Run the code directly on the chip, with excellent stability and high transmission rate, which is very suitable for embedded systems. As the advantage of NorFLASH ROM, it solves the problem that there are many control signals on the NorFLASH port, and the implementation of direct register control will consume a lot of CPU resources and operation steps Complicated problems; simple operation, consumes less CPU resources, and facilitates software development

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