C program to register transfer level (RTL) comprehensive method of pipeline division and module parallel optimization

Abstract

The invention relates to the technical field of hardware design automation, in particular to a C program to register transfer level (RTL) comprehensive method of pipeline division and module parallel optimization. A pipeline and a parallel structure are two most effective methods of improving hardware performance for a hardware design. The C-to-RTL comprehensive method of the pipeline division and the module parallel optimization includes that the pipeline division and the module parallel are simultaneously optimized in the process of C-to-RTL comprehensiveness, the optimized pipeline division and the optimized module parallel are obtained after a user gives system performance constraints; meanwhile, compared with a method of two optimization procedures to optimize step by step, the C-to-RTL comprehensive method guarantees global optimality. The C-to-RTL comprehensive method of the pipeline division and the module parallel optimization has the advantages of enhancing practicability and application range of the C-to-RTL comprehensive technology and providing forceful technical support for the hardware design.

Description

technical field [0001] The invention relates to the technical field of hardware design automation, in particular to a C-to-RTL synthesis method for pipeline division and module parallel optimization. Background technique [0002] C-to-RTL synthesis refers to the direct conversion of the C program at the algorithm description level to the HDL (Hardware Description Language) program at the transistor level (Register transfer level), which is a kind of high-level synthesis in hardware design automation. Through the C-to-RTL synthesis technology, the HDL design work that traditionally requires a lot of manual work can be quickly and automatically completed. Generally speaking, C-to-RTL synthesis has the following advantages: (1) It shortens the hardware design time and simplifies the design difficulty, which makes it a solution to the contradiction between the high-speed growth of hardware design requirements and the low-speed growth of design capabilities. Effective way; (2), ...

AI Technical Summary

Problems solved by technology

[0003] However, there are still many unresolved problems in the existing C-to-RTL synthesis technology, for example: (1), when synthesizing large-scale C programs, the quality of the synthesis results is not ideal; (2), users cannot The performance (throughput rate, area, etc.) to make optimization settings and given constraints

The root causes of these problems are mainly: the design and optimization of high-level or system-level hardware architecture has not been considered, and the C language cannot express the timing, parallelism, architecture, etc. in the hardware.

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