Optimizing method for shift power consumption in scanning test

Abstract

The invention discloses an optimizing method for shift power consumption in a scanning test. On the basis of basic test flow, the method comprises three steps of power consumption information extraction, power consumption sensitive unit selection and inserting test logic. The method disclosed by the invention can be used for greatly reducing the shift power consumption in the test process, and meanwhile, the test time is not increased, the test coverage rate is not influenced, the test design flow is not required to be changed, and moreover, the method is more easily realized.

Description

technical field [0001] The invention belongs to the technical field of chip low power consumption testing, and in particular relates to an optimization method for shift power consumption in scanning testing. Background technique [0002] With the continuous shrinking of the physical size of integrated circuits and the continuous reduction of voltage thresholds, power consumption, performance, and area have become the most important design indicators for system chip design. In the last decade, low-power design based on algorithms, architectures, and circuits has attracted great attention, and chip designers are increasingly adopting low-power designs to meet increasingly difficult power consumption challenges. While low-power design methodologies can address power consumption issues that arise in the design of complex digital systems, they are not very effective for power consumption in test modes. Studies have shown that the power consumption of LSI in test mode may reach m...

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Problems solved by technology

Similar to reducing the test clock frequency, this method also increases the test time

Moreover, this block test method needs to modify the circuit design, such as adding a multiplexer to select between multiple block signals, which leads to an increase in the complexity of the test design.

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