JTAG (joint test action group) debug method of multi-core processor

Abstract

The invention provides a JTAG (joint test action group) debug method of a multi-core processor. A multichannel test interface controller is connected between a standard test access port controller and a simulator JTAG debug interface of every processor core. The debug method comprises the following steps that: firstly, a system is electrified, and the functional state machine of the multichannel test access port controller enters the state of test logic reset; secondly, a debug command is sent, and specific TCK (testing clock), TDI (testing data input) and TMS (testing method select) signals are output through the simulator JTAG debug interface, so that state control modules enter states in sequence; thirdly, selective signals are sent, and a control register is configured; fourthly, after one-clock cycle of delay, the information in the control register is loaded to a state register; and fifthly, after finishing the selection of the processor cores, the debug command is sent, and the debug procedure of a single-core processor is carried out. The invention effectively completes the selection and the control of every processor core and the storage and the feedback of debug information, so that the reliability is promoted.

Description

technical field [0001] The invention relates to the technical field of JTAG standard-based debugging of a microprocessor chip, in particular to a JTAG debugging method for a multi-core processor. Background technique [0002] With the increasing demands on processing power and energy consumption, multi-core processors have become the main solution for current high-end processor chips. However, as the scale of the multi-core architecture increases, its design complexity also increases, which brings great challenges and difficulties to the online debugging of multi-core processors. The present invention cleverly designs the multi-channel test access port controller between the multi-core processor chip test interface and the JTAG debug interface of the emulator, effectively realizes the multiplexing of the emulator and debugging software for single-core debugging, and only for debugging The software adds instructions for selecting a certain core and viewing the corresponding ...

AI Technical Summary

Problems solved by technology

[0009] In order to overcome the shortcomings of the existing JTAG debugging method for multi-core processors that cannot effectively complete the selection control and debugging information storage feedback of each processor core and the poor reliability, the present invention provides a method for effectively completing the selection control and debugging information of each processor core. JTAG debugging method of multi-core processor with memory feedback and improved reliability

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