A method for gate replacement integration of semiconductor devices

Abstract

Disclosed is a method for integrating a substitute gate of a semiconductor device, which comprises: providing a semiconductor substrate; forming a well region on the semiconductor substrate, and defining an N-type device region and / or a P-type device region; forming a sacrifice gate stack in the N-type device region and / or the P-type device region respectively, the sacrifice gate stack comprising a sacrifice gate dielectric layer and a sacrifice gate electrode layer, the sacrifice gate dielectric layer being located on the semiconductor substrate, and the sacrifice gate electrode layer being located on the sacrifice gate dielectric layer; forming a side wall surrounding the sacrifice gate stack; forming a source / drain region which is located on two sides of the sacrifice gate stack and embedded in the semiconductor substrate; forming a SiO2 layer on the semiconductor substrate; spin coating SOG on the SiO2 layer; etching the SOG to expose the SiO2 layer; performing rate difference etching on the SOG and the SiO2 layer, to obtain a flat surface of the SiO2 layer; and subsequently, forming an N-type substitute gate stack in the N-type device region and / or forming a P-type substitute gate stack in the P-type device region.

Description

technical field [0001] The present invention relates to the technical field of ultra-deep submicron semiconductor devices, in particular to a method for gate replacement integration of high-k gate dielectric / metal gate semiconductor devices. The method uses sacrificial SiO 2 / Polysilicon gate is used as a sacrificial gate stack. After the planarization process, the sacrificial gate stacks in the N-type device region and the P-type device region are respectively removed to form a high-k gate dielectric / metal gate replacement gate stack to realize N-type and P-type high-k Integration of gate dielectric / metal gate semiconductor devices. Background technique [0002] For more than 40 years, integrated circuit technology has continued to develop according to Moore's law, with continuous shrinking of feature size, continuous improvement of integration, and increasingly powerful functions. Currently, the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) ...

AI Technical Summary

Problems solved by technology

However, this method has some insurmountable shortcomings: firstly, the metal gate electrode is easily penetrated by ions implanted into the source / drain, which affects the electrical characteristics of the device; The work function of most metal gate materials will move to the center of the forbidden band after high temperature annealing treatment, resulting in the degradation of device performance

However, this gate-last process also has certain shortcomings, mainly because it is easy to cause damage to the underlying high-k gate dielectric when removing the dummy gate electrode, reducing the reliability of the high-k gate dielectric

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