Packaging-first and etching-later manufacturing method for chip formal double-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit

A three-dimensional circuit, sealing first and etching later technology, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problems of great differences in material characteristics, stress deformation, and reliability levels that affect reliability and safety capabilities. Achieve the effects of not being easy to stress and deform, reducing environmental pollution, and improving safety

Active Publication Date: 2013-11-27
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019]3. Glass fiber itself is a kind of foaming material, so it is easy to absorb moisture and moisture due to the storage time and environment, which directly affects the reliability and safety ability or is the level of reliability;
[0020] 4. The surface of the glass fiber is covered with a copper foil metal layer thickness of about 50-100 μm, and the etching distance between the metal layer line and the line can only achieve an etching gap of 50-100 μm due to the characteristics of the etching factor (see Figure 124 , the best production capacity is that the etching gap is approximately equal to the thickness of the etched object), so it is impossible to truly design and manufacture high-density circuits;
[0022]6. Also because the entire substrate material is made of glass fiber, the thickness of the glass fiber layer is obviously increased by 100~150μm, and it cannot be really ultra-thin encapsulation;
[0023]7. Due to the large difference in material characteristics (expansion coefficient) of the traditional glass fiber plus copper foil technology, it is easy to cause stress deformation in the harsh environment process, directly Affects the accuracy of component loading and the adhesion and reliability of components and substrates

Method used

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  • Packaging-first and etching-later manufacturing method for chip formal double-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit
  • Packaging-first and etching-later manufacturing method for chip formal double-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit
  • Packaging-first and etching-later manufacturing method for chip formal double-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0136] Embodiment 1, no base island

[0137] Step 1. Take the metal substrate

[0138] see figure 1 , take a metal substrate with a suitable thickness, the material of the metal substrate can be changed according to the function and characteristics of the chip, for example: copper, iron, nickel-iron or zinc-iron;

[0139] Step 2. Pre-plating copper on the surface of the metal substrate

[0140] see figure 2 , electroplating a layer of copper film on the surface of the metal substrate, the purpose is to serve as a basis for subsequent electroplating, and the electroplating method can be electroless plating or electrolytic plating;

[0141] Step 3, green paint coating

[0142] see image 3 In step 2, the front and back of the metal substrate of the pre-plated copper film are covered with green paint to protect the subsequent electroplating metal layer process operations;

[0143] Step 4. Remove part of the green paint from the front of the metal substrate

[0144] see ...

Embodiment 2

[0212] Embodiment 2, there is base island

[0213] Step 1. Take the metal substrate

[0214] see Figure 38 , take a metal substrate with a suitable thickness, the material of the metal substrate can be changed according to the function and characteristics of the chip, for example: copper, iron, nickel-iron or zinc-iron;

[0215] Step 2. Pre-plating copper on the surface of the metal substrate

[0216] see Figure 39 , electroplating a layer of copper film on the surface of the metal substrate, the purpose is to serve as a basis for subsequent electroplating, and the electroplating method can be electroless plating or electrolytic plating;

[0217] Step 3, green paint coating

[0218] see Figure 40 In step 2, the front and back of the metal substrate of the pre-plated copper film are covered with green paint to protect the subsequent electroplating metal layer process;

[0219] Step 4. Remove part of the green paint from the front of the metal substrate

[0220] see Fi...

Embodiment 3

[0288] Embodiment 3, there is an electrostatic discharge ring with a base island

[0289] Step 1. Take the metal substrate

[0290] see Figure 75 , take a metal substrate with a suitable thickness, the material of the metal substrate can be changed according to the function and characteristics of the chip, for example: copper, iron, nickel-iron or zinc-iron;

[0291] Step 2. Pre-plating copper on the surface of the metal substrate

[0292] see Figure 76 , electroplating a layer of copper film on the surface of the metal substrate, the purpose is to serve as a basis for subsequent electroplating, and the electroplating method can be electroless plating or electrolytic plating;

[0293] Step 3, green paint coating

[0294] see Figure 77 In step 2, the front and back of the metal substrate of the pre-plated copper film are covered with green paint to protect the subsequent electroplating metal layer process operations;

[0295] Step 4. Remove part of the green paint from...

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Abstract

The invention relates to a packaging-first and etching-later manufacturing method for a chip formal double-surface three-dimensional circuit and a packaging structure of the chip formal double-surface three-dimensional circuit. The method comprises the following technology steps of taking a metal substrate; pre-plating copper on the surface of the metal substrate; coating the surface of the metal substrate with green paint; removing a part of the green paint from the front surface of the metal substrate; electro-plating an inert metal circuit layer; electro-plating a metal circuit layer; coating the front surface of the metal substrate with the green paint; removing a part of the green paint from the front surface of the metal substrate; electro-plating the metal circuit layer; coating the front surface of the metal substrate with the green paint; removing a part of the green paint from the front surface of the metal substrate; coating a circuit screen board; pre-processing of metallization; removing the circuit screen board; electro-plating the metal circuit layer; coating bonding materials; installing a chip; bonding with metal wires; packaging; removing a part of the green paint from the back surface of the metal substrate; chemical-etching; electro-plating the metal circuit layer; electro-plating the metal circuit layer; coating the back surface of the metal substrate with the green paint; tapping on surface of the green paint; cleaning; implanting a metal ball; and cutting a finished product. The method disclosed by the invention has the beneficial effects that the manufacturing cost is lowered, the safety and the reliability of a packaging body are increased, the environment pollution is reduced, and the design and the manufacturing of a high-density circuit can be really realized.

Description

technical field [0001] The invention relates to a method for manufacturing a double-sided three-dimensional circuit of a front-mounted chip by sealing first and etching later and the packaging structure thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] The manufacturing process flow of the traditional high-density substrate package structure is as follows: [0003] Step 1, see Figure 112 , take a substrate made of glass fiber material, [0004] Step two, see Figure 113 , opening holes at desired locations on the fiberglass substrate, [0005] Step three, see Figure 114 , coated with a layer of copper foil on the back of the glass fiber substrate, [0006] Step 4, see Figure 115 , fill the conductive material in the position where the glass fiber substrate is punched, [0007] Step five, see Figure 116 , coated with a layer of copper foil on the front of the glass fiber substrate, [0008] Step six, see Figure 1...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48H01L21/56H01L23/31C25D5/10C25D5/02C25D7/00
CPCH01L24/97H01L2924/01322H01L2924/15311H01L2224/97H01L2224/73265H01L2224/32245H01L2224/32013H01L2224/48247H01L24/73H01L2924/07802H01L2924/181
Inventor 王新潮李维平梁志忠
Owner JCET GROUP CO LTD
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