Split-gate memory device and forming method thereof

A storage device and a discrete gate technology, which is applied in the field of discrete gate storage devices and their formation, can solve the problems of reducing the barrier of the tunnel oxide layer, and achieve the effect of avoiding size deviation and improving uniformity

Inactive Publication Date: 2012-07-04
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

The Chinese patent application number 200610118219.7 discloses a method for forming a discrete gate storage device, but it fails to effectively solve the problem of lowering the barrier of the tunnel oxide layer

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  • Split-gate memory device and forming method thereof
  • Split-gate memory device and forming method thereof
  • Split-gate memory device and forming method thereof

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Embodiment Construction

[0057] In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0058] In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar promotions without departing from the connotation of the present invention. Accordingly, the present invention is not limited by the specific implementations disclosed below.

[0059] The method provided by the present invention is not only applicable to discrete gate flash memory devices, but also to general logic devices and storage devices. Especially suitable for MOS transistor structures with feature sizes of 130nm and below. The MOS trans...

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Abstract

The invention provides a forming method of a split-gate memory device. The forming method comprises the steps of: providing a substrate; forming two control gates on the substrate, wherein a region between the two control gates is an erasing gate region, and a region outside the two control gates is a word line region; forming a side wall and a sacrifice side wall which is arranged on the side surface of the side wall; using the sacrifice side wall as a mask to form a floating gate; removing the sacrifice side wall; and forming a tunneling oxide and an erasing gate, wherein the erasing gate and the floating gate have lateral overlapped parts. The invention additionally provides the split-gate memory device. By forming the lateral protruding part of the floating gate and enabling the erasing gate and the floating gate to have the lateral overlapped parts, the overlapped parts can effectively reduce the width of the potential barrier of the tunneling oxide and can improve information erasing speed. By etching a silicon oxide layer and a silicon nitride layer in one step to form a dual-layer side wall and using the dual-layer side wall as a gap layer between word lines and the floating gate, the process of the gap layer is simplified, the uniformity of the gap layer is improved and the writing uniformity is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a discrete gate memory device and a method for forming the same. Background technique [0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. Among storage devices, the development of flash memory (flash memory) is particularly rapid in recent years. Its main feature is that it can keep the stored information for a long time without powering on, and has many advantages such as high integration, fast access speed, easy erasing and rewriting, etc. The field has been widely used. [0003] The standard physical structure of flash memory is called the basic bit (bit). Usually, the gate and the conductive channel layer of MOS are separated by a gate insulating layer, which is usu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L21/28H01L27/115H01L29/423
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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