Automatic construction method for evaluation stimulus of multi-thread cross double-precision short-vector structure

Abstract

The invention discloses an automatic construction method for an evaluation stimulus of a multi-thread cross double-precision short-vector structure. The method comprises the following steps of: inputting a vector operation type to be evaluated and a vector length to be evaluated; automatically creating an empty assembly language file which serves as the evaluation stimulus; writing contents such as a multi-thread running initial code segment, an evaluation stimulus control structure, a multi-thread vector operation program segment, an evaluation stimulus synchronization structure, a data segment and a data segment initialization statement into the assembly language file; and forming the integral evaluation stimulus of the multi-thread cross double-precision short-vector structure. By the method, the evaluation stimulus can be automatically constructed in batches, a construction time length can be decreased, cost can be saved, evaluation stimulus development efficiency can be improved, a processor can be conveniently verified, and the performance of the process can be conveniently evaluated.

Description

technical field [0001] The invention relates to the field of processors and the field of evaluation, in particular to a method for automatically constructing evaluation incentives for multi-thread interleaving double-precision short vector structure processors. Background technique [0002] With the increasing integration of processor chips, it is an important development trend to implement double-precision short vector components in processor cores to support data-intensive scientific and engineering calculations. Extending the double-precision short vector unit in the multi-thread processor core can greatly improve the double-precision floating-point computing capability of the processor. The double-precision short vector component needs to implement a short vector register with a longer word length (currently Intel's AVX already supports a 256-bit short vector with a total of 4 double-precision data), and needs to implement a corresponding vector operation instruction set...

AI Technical Summary

Problems solved by technology

In the process of processor verification and performance evaluation, it is necessary to write a large number of assembly language programs as evaluation incentives. Usually, these programs are manually written by R&D and testers, and the workload is heavy and time-consuming.

Due to different processor instruction set architectures and different short vector extension methods, it is impossible to inherit and reuse the existing evaluation incentives for multi-threaded short vector processing functional units

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