Memory structure
A memory and composite structure technology, applied in the field of split-gate flash memory structure, can solve the problem of device programming voltage reduction and achieve the effect of avoiding over-erasing and reducing the area
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no. 2 Embodiment approach
[0040] figure 2 It is a structural schematic diagram of the second specific embodiment of the memory structure provided by the present invention.
[0041] Such as figure 2 As shown, the memory structure 200 provided in this specific embodiment includes: a semiconductor substrate 10 having a first active region 11 and a second active region 12 arranged at intervals thereon; a word line 303 located on the upper surface of the semiconductor substrate 10 , between the first active region 11 and the second active region 12; the first storage bit cell 110 is located between the word line 303 and the first active area 11; the second storage bit cell 210 is located between the word line 303 and the Between the second active region 12; wherein: the first storage bit cell 110 has a first floating gate 101 and a first control gate 102, and the first control gate 102 is arranged on the first floating gate 101 at intervals; the second The storage bit unit 210 has a second floating gate...
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