Time sequence verification method for standard cell library model

Abstract

The invention provides a time sequence verification method for a standard cell library model. The method comprises a step of verifying time sequence information on a coordinate point and / or an interpolation point of the standard cell library model by circuit simulation. The method provides the method for verifying the time sequence information of a library model file after the library model file is established. By using the method, the inaccurate time sequence information in the library model file can be corrected in the development process of the library, and each coordinate point in a search table can be accurately verified.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a timing verification method for a standard cell library model. Background technique [0002] In semi-customized IC (Integrated Circuit, integrated circuit) design, the standard cell library is the link between the actual chip and the designed circuit. For digital circuit design, especially for large-scale digital circuit design in the nanotechnology stage, the standard cell library has become a necessary condition for designing circuits. refer to figure 1 , figure 1 It is shown that the entire digital circuit design process is supported from behavioral description to post-simulation with delay information. [0003] As the chip scale becomes more and more complex and the process size shrinks day by day, the problem of timing closure will undoubtedly become more and more complicated and unavoidable. The library model file (.lib file) that reflects the timing informatio...

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Problems solved by technology

[0006] Although the methods in the prior art can effectively verify the timing information of the cells in the cell library, the cost of tape-out is very high, and the tape-out verification cycle is long and the number of iterations is large

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