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FPGA (field-programmable gate array)-based high-speed FIR (finite impulse response) digital filter

A digital filter and filter technology, applied in the direction of digital technology network, impedance network, electrical components, etc., can solve the problem of reduced computing speed, achieve the effect of increasing computing speed, improving computing efficiency, and saving computing delay

Inactive Publication Date: 2012-02-15
BEIHANG UNIV
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Problems solved by technology

Obviously, the delay of this structure increases rapidly with the increase of the filter order, which reduces the operation speed

Method used

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  • FPGA (field-programmable gate array)-based high-speed FIR (finite impulse response) digital filter
  • FPGA (field-programmable gate array)-based high-speed FIR (finite impulse response) digital filter
  • FPGA (field-programmable gate array)-based high-speed FIR (finite impulse response) digital filter

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Embodiment Construction

[0024] specific implementation plan

[0025] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.

[0026] Such as figure 1 As shown, the improved FIR filter structure can be implemented with a 3-stage pipeline. The Booth encoding module and the partial product adder array module are used as the first stage of the pipeline design, and the Wallace addition tree for data compression and addition is used as the second stage of the pipeline design. stage, the final adder is used as the third stage of the pipeline design, and the three-stage pipeline is sequentially connected in series through registers.

[0027] The shift register continuously sends the multiplier to the Booth encoder for encoding, and the 3 control signals generated together with the multiplicand A are input to the partial product generator to generate 5 different partial products, namely "0A", "0A", "-A", "+A", "-2A" and "+2A", all the partial p...

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Abstract

An FPGA-based high-speed FIR digital filter is characterized in that an improved Booth coding mode and a partial product adder array module are used as the first stage of the pipeline design; a Wallace adder tree for compressing and adding 2M data is used as the second stage of the pipeline design; and a final adder is used as the third stage of the pipeline design. The order number and coefficient of the filter can be adjusted conveniently by reasonably partitioning a high-speed multiplier and combining the Wallace adder tree array through the pipeline technology, so that the FPGA-based high-speed FIR digital filter is applicable to different occasions and the operation speed is improved greatly.

Description

technical field [0001] The invention relates to an FIR digital filter, in particular to a high-speed FIR filter realized on FPGA by adopting pipeline technology. Background technique [0002] The FIR filter is a widely used basic digital signal processing component. It can have strict linear phase-frequency characteristics while ensuring arbitrary amplitude-frequency characteristics. At the same time, its unit impulse response is limited, there is no feedback from input to output, and it is a stable system. Therefore, FIR filters are widely used in communication, image processing, pattern recognition and other fields. [0003] However, in some systems with high real-time requirements such as radar control or wireless communication, due to the sequential execution of the program, the traditional direct FIR filter structure can no longer meet the requirements of high-speed systems. tor circuit limitations. The time delay of the direct form structure of the FIR filter is T ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/02
Inventor 王俊栾军袁运能
Owner BEIHANG UNIV
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