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Method for reducing area of digital logic circuit

A technology of digital logic circuits and areas, applied in the direction of logic circuits using basic logic circuit components, logic circuits using specific components, etc.

Inactive Publication Date: 2011-09-14
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

but even for figure 1 The circuit shown is simplified by the method shown in formula (2), and there is the possibility of further reduction

Method used

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  • Method for reducing area of digital logic circuit
  • Method for reducing area of digital logic circuit
  • Method for reducing area of digital logic circuit

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Embodiment

[0033] A method to reduce the area of ​​digital logic circuits, the logic function to be optimized is defined as f , f The optimized function is defined as f op ; f The set of product terms of is defined as S p ;like S p contains w product terms, any one of which is defined as p i ; D pi represents the product term p i The dimensionality of , that is, for a n function of variables, if the logistic function f a product of p i contain m variables, m≤n ,but p i The dimension of D pi =( n-m ); and order f op The initial value of is "0" and the specific steps are:

[0034] step a. Define the generalized Hamming distance: for a given n logistic function of variables f , and any two product terms of it are ,in i and j None greater than w; the product term p i and p j The generalized Hamming distance between p i and p j The difference between the values; the generalized Hamming distance is equal to the number of variables that meet the follo...

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Abstract

The invention discloses a method for reducing area of a digital logic circuit. By utilizing the characteristic of xor operation, a specified product term is generated and added into the optimized function; owning to the adding of the new product term, the original product term with nonadjacent logics becomes logically adjacent owning to the interposing of the product term, thus realizing logic optimization; the method has the advantages that after the existence of two product terms with the generalized hamming distance of 2 is judged, the two product terms do not form an xor expression immediately; a corresponding addition term is generated; and subsequently whether the addition term is suitable for function simplification is judged by a corresponding evaluation method. As the complexity of the logic function is related to the complexity of the corresponding digital circuit, the simple logic function always corresponds to a smaller circuit area; and the aim of reducing the area of digital logic circuit can be achieved by the method of simplifying logic function.

Description

technical field [0001] The invention relates to a method for optimizing a digital logic circuit, in particular to a method for reducing the area of ​​a digital logic circuit. Background technique [0002] A very important link in integrated circuit design is the logic synthesis and optimization of the circuit. In logic synthesis and optimization, one of the indicators is how to control the area of ​​the integrated circuit. Considering that the complexity of the logic function is closely related to the complexity of the corresponding digital circuit, a simple logic function often corresponds to a smaller circuit area, so the area of ​​the logic circuit can often be reduced by simplifying the logic function. [0003] The logic function representation of digital circuits can be realized by Boolean logic based on AND / OR / NOT operation, and can also be realized by AND / XOR logic. However, almost all the digital electronic design automation software (Electronic Design Automation, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/173
Inventor 王伦耀夏银水
Owner NINGBO UNIV
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