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Implementation method of adaptive clock holdover mode and device thereof

A technology of hold mode and implementation method, applied in time division multiplexing systems, digital transmission systems, data exchange networks, etc., can solve problems such as false triggering of adaptive clock hold mode, and achieve the effect of solving the problem of false triggering

Inactive Publication Date: 2011-03-09
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a method and device for implementing an adaptive clock hold mode, which effectively solves the problem of false triggering of the adaptive clock hold mode

Method used

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  • Implementation method of adaptive clock holdover mode and device thereof
  • Implementation method of adaptive clock holdover mode and device thereof
  • Implementation method of adaptive clock holdover mode and device thereof

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Embodiment Construction

[0027] Can cause the CDVT FIFO to underflow. In addition to network interruptions, the adaptive clock has not yet locked the source clock and is faster than the source clock. It may also cause the CDVT FIFO to underflow. Underflow in this case should not trigger the adaptive clock to enter hold mode , instead keep the adaptive clock in tracking mode to lock to the source clock as soon as possible. Currently, the CDVT FIFO underflow event is commonly used in the industry to trigger the adaptive clock to enter the hold mode. The disadvantage is that it does not distinguish whether the underflow event is caused by a network interruption or because the adaptive clock has not yet locked the source clock. The basic idea of ​​the present invention is to further judge whether the root cause of the underflow is network interruption or the adaptive clock has not locked the source clock after detecting the CDVT FIFO underflow event, and decide whether to trigger the adaptive clock to ente...

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Abstract

The invention provides an implementation method of adaptive clock holdover mode and a device thereof. The method includes: cell delay variation tolerance first input first output (CDVTFIFO) buffer underflow event is detected, if no new time division multicomplex service pay load is received within preset time, an adaptive clock is triggered to be in holdover mode. By adopting the invention, the problem of false triggering of adaptive clock holdover mode can be effectively solved.

Description

technical field [0001] The invention relates to the application field of network carrying TDM services, in particular to a method and device for realizing an adaptive clock holding mode. Background technique [0002] Synchronous Digital Hierarchy (SDH) has been proposed for 20 years. As a mainstream transmission technology, it has played an important role in telecommunication networks. However, SDH is a transmission technology system designed for circuit-type services represented by voice. Today, when IP is the dominant service, SDH has become unsuitable in terms of efficiency and flexibility. The telecommunications industry started research on the next-generation transport network a few years ago. In order to solve this problem, PTN technology came into being. It supports a variety of bidirectional point-to-point connection channels based on packet switching services, and has end-to-end networking capabilities suitable for various coarse-grained services. It can be comple...

Claims

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Application Information

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IPC IPC(8): H04J3/06H04L12/56
CPCH04J3/0632H04J3/0688H04J3/0697
Inventor 尹景鹏
Owner ZTE CORP
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