Test method on failure analysis of storage cell

Abstract

The invention provides a test method on failure analysis of a storage cell, which comprises the steps of defining an internal storage region, in which the number and the position of internal storage cells correspond to storage cells on a chip; pressurizing the storage cells in the adjustable value range and measuring the storage cells to obtain threshold voltages of the storage cells, storing step value information related to the threshold voltage into an internal storage position which corresponds to the internal storage region until threshold voltages of all storage cells can be tested; reading out the step value information related to the threshold voltages in the internal storage region to generate a data file; and analyzing the data file to obtain information of the threshold voltages corresponding to the storage cell position, and calculating the information of threshold voltage distribution of a whole storage chip at the same time. The method can be used for accurately positioning the failure point of the threshold voltage, so as to improve the test efficiency.

Description

technical field [0001] The invention relates to the testing field of semiconductor devices, in particular to a testing method for failure analysis of storage units. Background technique [0002] The storage unit is used to store or temporarily store the data and calculation results involved in the calculation, and has been widely used in electronic communication products. With the development of ASIC design technology, more and more storage units have been embedded or plugged into ASIC and FPGA chips. However, in the ASIC and FPGA logic code design, some failures often occur in the storage unit, such as incorrect reading and writing functions of the storage unit or the data of a storage unit is changed due to the influence of data or read and write operations of other units. Therefore, it is very important to carry out project testing on the storage unit. [0003] Before mass production and during the development of new memory cell arrays, testing can include measuring the...

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Problems solved by technology

[0005] However, due to the large number of memory cells on a chip, the position of the failed memory cell cannot be accurately located according to the threshold voltage distribution state diagram, and thus the physical failure analysis of the memory cell cannot be performed, and it is also difficult to achieve a test yield rate. promote

[0006] And as figure 2 As shown, the good / bad bitmap of each storage unit can be obtained through the "read" function of the memory chip, so that the failure location of the storage unit can be located, but the specific threshold voltage value of the failure point cannot be determined, and it is difficult to know more about it. Failure condition

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