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Flying scoreboard device for controlling out-order transmission in superscale microprocessor

A microprocessor and scoreboard technology, applied in machine execution devices, concurrent instruction execution, etc., can solve the problems of waste of area and power consumption, long delay of physical register state table, etc., to reduce area and power consumption, The effect of shortening the critical path delay and improving the energy consumption ratio

Active Publication Date: 2012-07-18
上海高性能集成电路设计中心
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AI Technical Summary

Problems solved by technology

The traditional out-of-sequence control device sets up m-bit scoreboards, and each bit corresponds to a physical register. At any time, at least n-bit scoreboards are not functioning, which means that there is a waste of area and power consumption, and access to physical The latency of the register state table is also very long

Method used

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  • Flying scoreboard device for controlling out-order transmission in superscale microprocessor
  • Flying scoreboard device for controlling out-order transmission in superscale microprocessor
  • Flying scoreboard device for controlling out-order transmission in superscale microprocessor

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Embodiment Construction

[0014] Such as figure 1 As shown, the device of the present invention needs to set a flight scoreboard mapping table and a flight scoreboard recovery list at the register renaming station, and set a flight scoreboard status table at the launch station.

[0015] Such as figure 2 As shown, the flight scoreboard mapping table records the nearest mapping relationship between logic registers and flight scoreboards. The number of entries is equal to the number of logic registers (n). scoreboard with log 2 (m-n) bit representation. If the effective bit is "0", it means that the source register of the instruction has already been prepared, and there is no need to query the flight scoreboard status table when the instruction is launched; It is necessary to query the flight scoreboard status table.

[0016] Such as figure 2 As shown, the flight scoreboard recovery list records the last mapping relationship between the target logic registers of all flight instructions and the flig...

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Abstract

The invention discloses a flying scoreboard device for controlling out-order transmission in a superscale microprocessor, comprising a flying scoreboard mapping table, a flying scoreboard recovering list and a flying scoreboard state table. For an effective command of a target register, the device tracks the state of the command target register dynamically; for an effective command of a source register, the device provides information whether the command source register is readable in real time to judge whether the command can be transmitted to an executive component. The device solves read-after-write relevance caused by use of a register between commands through less hardware resources, ensures accuracy of out-order transmission and execution of commands, and improves the energy consumption ratio of the microprocessor.

Description

technical field [0001] The invention relates to the instruction pipeline design of a superscalar microprocessor. Background technique [0002] The instruction pipeline is the core part of the microprocessor, and its performance is very important. The current superscalar microprocessor instruction pipeline supports out-of-order launch and out-of-order execution. The instruction pipeline usually includes several basic pipeline platforms such as fetching, decoding, register renaming, launching, reading registers, executing, and exiting. The register renaming and launching platform are the parts with the highest technical content on the instruction pipeline, and the largest proportion of area and power consumption, which directly affects the energy consumption ratio of the instruction pipeline. [0003] The instruction uses a logical register, and two instructions before and after write the same logical register, indicating that there is a write-after-write correlation between ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/30
Inventor 尹飞
Owner 上海高性能集成电路设计中心
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