Nonvolatile memory device and method for manufacturing the same

Abstract

Embodiments relate to a nonvolatile memory device and a method for manufacturing the same. According to embodiments, a nonvolatile memory device may include a tunnel ONO film having an oxide film, a nitride film, and an oxide film stacked on and / or over a semiconductor substrate. It may also include a trap nitride film formed on and / or over the tunnel ONO film, a blocking oxide film formed on and / or over the trap nitride film and having a high-dielectric film with a higher dielectric constant than a dielectric constant of a SiO2 film. According to embodiments, a gate may be formed on and / or over the blocking oxide film. An electron back F / N tunneling at the time of an erase operation may be minimized. This may improve an erase speed and erase Vt saturation phenomenon.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2007-0139622 (filed on December 28, 2007) based on 35 U.S.C119, the entire contents of which are hereby incorporated by reference. technical field [0002] The present invention relates to a nonvolatile memory device (nonvolatile memory device) and its manufacturing method, more particularly, to a device with a silicon-oxide-nitride-oxide-nitride-oxide-silicon (SONONOS) structure Or a quantum well nonvolatile memory device with a bandgap engineered (Bandgap Engineered) SONOS (BE-SONOS) structure and a manufacturing method thereof. Background technique [0003] The nonvolatile memory device may be a floating gate based nonvolatile memory device. When adjusting the nonvolatile memory device based on the floating gate to a size of no more than 60nm, due to the cell-to-cell interference effect (interference effect), the cell-to-cell V t The distribution may be relatively large. This may lead to error...

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Problems solved by technology

Therefore, in a memory device with a SONONOS or BE-SONOS structure, there may be a limitation in increasing the erasing speed

Additionally, the erased state in the V t may not drop down to erase V t below a predetermined value, which may limit the implementation of multi-level bit (multi-level bit)

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