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Semiconductor device and its manufacturing method

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of insufficient cost and expensive manufacturing, and achieve the effect of high withstand voltage and low on-resistance

Inactive Publication Date: 2009-06-24
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0026] However, in order to realize the LDMOS transistor described in the well-known document 2, the epitaxial layer 102 must be formed during the manufacturing process, so a special epitaxial manufacturing unit becomes necessary, and thus, there is a disadvantage in terms of cost, so that the manufacturing becomes more expensive

Method used

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  • Semiconductor device and its manufacturing method
  • Semiconductor device and its manufacturing method
  • Semiconductor device and its manufacturing method

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no. 1 approach

[0077] will refer to Figure 1-8 The device and method of the present invention according to the first embodiment mode (hereinafter occasionally referred to as "the present embodiment mode") are described.

[0078] figure 1 is a schematic plan view showing a semiconductor device of the present invention according to this embodiment mode. also, figure 2 is showing figure 1 An enlarged view and a schematic cross-sectional view of a part of a device of the present invention are shown. Here, the cross-sectional view schematically shows the structure, and the dimensions in the drawings do not necessarily match the actual ones. The same is true in the following embodiments. Additionally, with Figure 19 to Figure 2 Components that are the same as those in 2 are denoted by the same symbols throughout the drawings.

[0079] exist figure 1 and 2 The device 10 of the present invention shown in is composed of P-type semiconductor substrate 1, N-type well region 2, P-type bod...

no. 2 approach

[0103] will refer to Figure 9-1 2 Describe the device and method of the present invention according to the second embodiment (hereinafter referred to as "the present embodiment").

[0104] Figure 9 is a schematic plan view showing a device of the present invention according to this embodiment mode. also, Figure 10 is showing Figure 9 An enlarged view and a schematic cross-sectional view of a part of a device of the present invention are shown. Here, the same components as those in the first embodiment are denoted by the same symbols, so descriptions thereof will not be given here.

[0105] Such as Figure 9 and 10 As shown, the device 10 a of the present invention according to this embodiment differs from the first embodiment in that the body region 3 is formed to surround the drain region 8 . The rest of the configuration is similar to that in the first embodiment.

[0106] The present embodiment has a structure in which the drain region 8 is formed in the central...

no. 3 approach

[0119] will refer to Figure 13 and 14 A device and method of the present invention according to a third embodiment mode (hereinafter referred to as "this embodiment mode") are described.

[0120] Figure 13 are a schematic plan view and a schematic cross-sectional view showing a device of the present invention according to this embodiment mode. Here, the same components as those in the first and second embodiments are denoted by the same symbols, so descriptions thereof will not be given here.

[0121] Such as Figure 13 As shown, the device 10b of the invention according to this embodiment is formed in such a way that the body region 3 surrounds the drain region 8, as in the device 10a of the invention according to the second embodiment. Furthermore, as in the second embodiment, P-type buried diffusion region 4 is formed so as to be in contact with the bottom of body region 3 , and P-type buried diffusion region 4 extends to a region below drain region 8 . Furthermore, ...

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Abstract

Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area (2) formed on a P-type semiconductor substrate (1), a P-type body area (3) formed within the well area (2), an N-type source area (6) formed within the body area (3), an N-type drain area (8) formed at a distance from the body area (3) within the well area (2), a gate insulating film (12) formed so as to overlay a part of the body area (3), a gate electrode (9) formed on the gate insulating film (12) and a P-type buried diffusion area (4) which makes contact with the bottom of the body area (3) and extends to an area beneath the drain area (8) in a direction parallel to the surface (1) of the semiconductor substrate within the well area (2).

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method, and particularly to an LDMOS transistor (lateral double-diffused MOS transistor) and its manufacturing method. Background technique [0002] Semiconductor devices having circuits such as switching regulators and DC / DC converters are used in various applications, and thus it has become necessary to increase the output current of the semiconductor devices. Therefore, LDMOS transistors having low on-resistance have attracted attention as a possible means of improving the performance of output current. [0003] The LDMOS transistor has a configuration in which impurities of a conductivity type different from those of the diffusion regions formed on the surface of the semiconductor substrate are diffused to form new diffusion regions and the difference in the diffusion lengths of these diffusion regions in the lateral direction is used as an effective channel track length...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0878H01L29/66681H01L29/7816H01L29/42368H01L29/1095H01L29/0696H01L29/0634
Inventor 一条尚生A·阿丹成濑一史键泽笃
Owner SHARP KK
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