Processing method and apparatus of iterative algorithm

An iterative algorithm and processing method technology, applied in complex mathematical operations, etc., can solve the problems of state machine state increase and decrease control errors, lack of versatility, etc., and achieve the effect of simplifying design, reducing coupling degree, independent development and easy verification

Active Publication Date: 2009-05-20
HUAWEI TECH CO LTD
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Problems solved by technology

[0006] Based on the control mode of the finite state machine, the iterative logic architecture is heavily dependent on the specific module structure of the iterative algorithm and the number of iterations, which lacks versatility; moreover, the increase or decrease of the iterative algorithm module or the number of iterations is prone to cause changes in the state of the state machine. potential control error

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  • Processing method and apparatus of iterative algorithm
  • Processing method and apparatus of iterative algorithm
  • Processing method and apparatus of iterative algorithm

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Embodiment Construction

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0026] The iterative algorithm processing device provided by the embodiment of the present invention controls the flow of the iterative algorithm based on the pre-stored command word mode, so that the iterative logic architecture is independent of the iterative algorithm module and the number of iterations, and provides a general logic architecture to solve most similar iterations. Implementation of the algorithm in an FPGA or ASIC device. The pr...

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Abstract

The embodiment of the invention discloses a method for processing iterative algorithm and a device thereof. The method comprises the following steps: each operation unit of the iterative algorithm is cascaded to form an operation chain in a serial connection mode; according to preset flow of the iterative algorithm, a command word is controlled; the operation unit for executing operation is selected from the operation chain; the flow direction of data in the operation process is determined; and based on the determined operation unit and the flow direction of the data, data needing iterative algorithm is subjected to operation processing. By adopting the embodiment, the flow of the iterative algorithm is controlled based on a mode of the prestored command word in order that an iterative logical framework has universality.

Description

technical field [0001] The invention relates to the field of digital communication, in particular to an iterative algorithm processing method and device. Background technique [0002] In digital signal processing, it is often necessary to perform multiple identical operations on the same or several cascaded computing modules, and use the output of this iteration as the input of the next iteration (such as clipping based on multiple iterations). Algorithm), the traditional digital signal processor (Digital Signal Processor, DSP) can realize this kind of iterative algorithm. [0003] However, with the sharp increase in the processing speed and bandwidth requirements of the algorithm, especially the algorithm that needs to perform high-speed and large-scale Fast Fourier Transform (FFT) and its inverse transform (InverseFast Fourier Transform, IFFT) , the system performance requirements are very high, and it is difficult for general-purpose DSP processors to achieve this requir...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/10G06F17/14
Inventor 朱江
Owner HUAWEI TECH CO LTD
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