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Error protection method, tdc module, ctdc module, and calibration method thereof

A time-to-digital conversion, all-digital phase-locked loop technology, applied in the direction of analog/digital conversion, code conversion, instruments, etc., can solve the problems of error propagation, and the analog phase-locked loop is prone to errors, and achieves the effect of reducing errors.

Inactive Publication Date: 2009-04-22
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] As known to those skilled in the art, because the analog PLL uses analog components and operates in an analog manner, the above-mentioned analog PLL is prone to error, or even error propagation (Errorpropagation)

Method used

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  • Error protection method, tdc module, ctdc module, and calibration method thereof
  • Error protection method, tdc module, ctdc module, and calibration method thereof
  • Error protection method, tdc module, ctdc module, and calibration method thereof

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Embodiment Construction

[0025] The present invention discloses an all-digital phase-locked loop for direct frequency modulation and having fine gaincalibration (Fine gaincalibration), wherein the all-digital phase-locked loop uses some components disclosed by the inventor (such as the disclosed by the inventor digitally controlled oscillator) with technical characteristics. Through the all-digital phase-locked loop disclosed in the present invention, the switching noise can be greatly reduced, and the loop gain of the all-digital phase-locked loop can also be precisely fine-tuned. Through the numerically controlled oscillator disclosed in the present invention, precise frequency resolution can be achieved in the disclosed all-digital phase-locked loop.

[0026] Please refer to FIG. 1 , which is a schematic diagram of an all-digital phase-locked loop 100 disclosed in an embodiment of the present invention. As shown in FIG. 1 , an all-digital phase-locked loop 100 includes a time-to-digital converter ...

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Abstract

For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Description

technical field [0001] The present invention relates to an error prevention method, a time-to-digital converter module, a cyclic time-to-digital converter module, an all-digital phase-locked loop, and a calibration method, and in particular to an error Prevention method, time-to-digital converter module applying the error prevention method, circular time-to-digital converter module, all-digital phase-locked loop including the time-to-digital converter module, and loop for calibrating the all-digital phase-locked loop The gain calibration method, wherein the time-to-digital converter module included in the all-digital phase-locked loop includes a circular time-to-digital converter module. Background technique [0002] A phase-locked loop is an electronic control system used to generate a signal that has a fixed relationship to the phase of a reference signal. The phase-locked loop circuit responds to the frequency and phase of the input signal, and automatically increases or...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08H03L7/18H03L7/099H03M1/50H03M3/02
Inventor 张湘辉詹景宏谢秉谕
Owner MEDIATEK INC
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